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Part: IS32WV16200
Category:
Memory
-> SRAM
-> Pseudo SRAM
Description: 32M2Mx16
Company: Integrated Silicon Solution Inc.
Datasheet: Download IS32WV16200 datasheet File size : 163 kB
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Datasheet text preview:
IS32WV16100A/B IS32WV16200A/B
1M x 16 (16-MBIT) , 2M x16 (32-MBIT) PSEUDO STATIC RAM
FEATURES
· Access time: 70ns · TTL compatible inputs and outsputs;tri-state I/O · Wide Power supply voltage: 1.65V to 2.2V (A) 2.2V to 3.6V (B) · CMOS Standby 60µA (16-MBIT) 70µA (32-MBIT) · Deep Power Down Standby 5µA (16-MBIT) 5µA (32-MBIT) · Deep Power-Down Mode: Data Invalid · Page Operation Mode: Four Word Access · Logic compatible with SRAM R/W (WE) pin. · Industrial Temperature Range: -40oC to 85oC · Page 48 pin FBGA (6mm x 8mm)
ISSI
ADVANCED INFORMATION JANUARY 2003
®
DESCRIPTION
The ISSI IS32WV16100A/B and IS32WV16200A/B are high-performance CMOS Pseudo Static RAM organized as a 1Meg x16, 2Meg x16, bits respectively. ISSI CMOS technology provides high density, high speed low power devices that features SRAM-like write timing. Data is written to memory cells on the rising edge of the WE signal. With a page size of 4 words, the device has a page access operation. The device also supports deep powerdown mode providing low-power standby. The IS32WV16100A/B and IS32WV16200A/B are packaged in a 48 pin FBGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A1 A2-A20/A21
DECODER
1Mb x16 2Mb x 16 MEMORY ARRAY
VD D GND I/O DATA CIRCUIT
I/O1-I/O16
COLUMN I/O
UB LB CE CS WE OE
CONTROL CIRCUIT
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. 00B 01/20/03
1
IS32WV16100A/B IS32WV16200A/B
PIN CONFIGURATIONS IS32WV16100A/B (48-pin BGA)
ISSI
IS32WV16200A/B (48-pin BGA)
®
1 A B C D E F G H
A4 A3 A2 A1 A0 CE OE GND
2
A17 A7 A6 A5 I/O1 I/O9 I/O10 I/O2
3
UB LB A18 NC I/O3 I/O11 I/O12 I/O4
4
CS WE NC A19 I/O6 I/O13 VDD I/O5
5
A8 A9 A10 A11 I/O8 I/O15 I/O14 I/O7
6
A12 A13 A14 A15 A16 NC I/O16 GND
1 A B C D E F G H
A4 A3 A2 A1 A0 CE OE GND
2
A17 A7 A6 A5 I/O1 I/O9 I/O10 I/O2
3
UB LB A18 NC I/O3 I/O11 I/O12 I/O4
4
CS WE A20 A19 I/O6 I/O13 VDD I/O5
5
A8 A9 A10 A11 I/O8 I/O15 I/O14 I/O7
6
A12 A13 A14 A15 A16 NC I/O16 GND
PIN DESCRIPTIONS
A0-A21 A0-A1 WE OE CE CS LB, UB VDD GND NC Address Inputs Page Address Inputs Write Enable Output Enable Chip Enable Input Chip Select Input Lower & Upper Data Byte Control Input Power Ground No Connection
I/O1 to I/O16 Data Input/Outputs
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. 00B 01/20/03
IS32WV16100A/B IS32WV16200A/B
TRUTH TABLE
Function Read: Word Read: Lower Byte Read: Upper Byte Write: Word Write: Lower Write: Upper Outputs Disabled Standby Deep Power-Down Standby CE L L L L L L L H H CS H H H H H H H H L OE L L L X X X H X X WE H H H L L L H X X LB L L H L L H X X X UB L H L L H L X X X
ISSI
ADD I/O1 to I/O8 I/O9 to I/O16 Power XX XX XX XX XX XX XX X X I / OO U T I / OO U T HIGH-Z DI N DI N INVALID HIGH-Z HIGH-Z HIGH-Z I / OO U T HIGH-Z I / OO U T DI N INVALID DI N HIGH-Z HIGH-Z HIGH-Z IC C1 IC C1 IC C1 IC C1 IC C1 IC C1 ISB ISB I SB 3
®
L = VIL, H =VIH, X = VIL or VIH, High-Z = High-impedence. XX = At CE falling edge, all addresses (A2 to A20) are valid "IN". Page address signals (A0 and A1) must be VIH or VIL, during entire cycle.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. 00B 01/20/03
3
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