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Part: IS61SP25618-5TQI
Category:
Memory
-> SRAM
-> Sync. SRAM
Description: 256Kx18
Company: Integrated Silicon Solution Inc.
Datasheet: Download IS61SP25618-5TQI datasheet File size : 468 kB
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Datasheet text preview:
IS61SP25616 IS61SP25618
256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM
FEATURES
· Internal self-timed write cycle · Individual Byte Write Control and Global Write · Clock controlled, registered address, data and control · PentiumTM or linear burst sequence control using MODE input · Three chip enables for simple depth expansion and address pipelining · Common data inputs and data outputs · JEDEC 100-Pin TQFP and 119-pin PBGA package · Single +3.3V, +10%, -5% power supply · Power-down snooze mode
ISSI
®
APRIL 2001
DESCRIPTION The ISSI IS61SP25616 and IS61SP25618 is a high-speed
synchronous static RAM designed to provide a burstable, high-performance memory for high speed networking and communication applications. It is organized as 262,144 words by 16 bits and 18 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQ1-8, BW2 controls DQ9-16, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol t KQ tKC Parameter Clock Access Time Cycle Time Frequency -166 3.5 6 166 -150 3.8 6.7 150 -133 4 7.5 133 -5 5 10 100 Units ns ns MHz
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/17/01
1
IS61SP25616 IS61SP25618
BLOCK DIAGRAM
ISSI
®
MODE ADV CLK
BURST COUNTER
ADSC ADSP A2-A17 A1 A0 2 18 16 CLK2 CLR
2
18
256K x 16/256K x 18 MEMORY ARRAY
ADDRESS REGISTER
GW
16 or 18
16 or 18
BWE
BW1
BW1 BYTE WRITE REGISTER
BW2
BW2 BYTE WRITE REGISTER
2
CLK
DATA INPUT REGISTER
DATA OUTPUT REGISTER
CLK2
CLK
CE1 CE2 CE2
ENABLE REGISTER
ENABLE REGISTER
OE
DQ1 - DQ16 or DQ1 - DQ18
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/17/01
IS61SP25616 IS61SP25618
PIN CONFIGURATION
119-pin PBGA (Top View) 100-Pin TQFP
ISSI
A6 A7 CE CE2 NC NC BW2 BW1 CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9
®
1 A VCCQ B NC C NC D DQ9 E NC F VCCQ G NC H DQ12 J VCCQ K NC L DQ14 M VCCQ N DQ16 P NC R NC T NC U VCCQ
2
3
4
5
6
7
A6 CE2 A7 NC DQ10 NC DQ11 NC VCC DQ13 NC DQ15 NC NC A5 A11 NC
A4 A3 A2 GND GND GND BW2 GND NC GND GND GND GND GND MODE A10 NC
ADSP ADSC VCC NC CE OE ADV GW VCC CLK NC BWE A1 A0 VCC NC NC
A8 A9 A12 GND GND GND GND GND NC GND BW1 GND GND GND NC A14 NC
A16 CE2 A15 NC NC DQ7 NC DQ5 VCC NC DQ3 NC DQ2 NC A13 A17 NC
VCCQ NC NC NC DQ8 VCCQ DQ6 NC VCCQ DQ4 NC VCCQ NC DQ1 NC ZZ VCCQ
NC NC NC VCCQ GND NC NC DQ9 DQ10 GND VCCQ DQ11 DQ12 NC VCC NC GND DQ13 DQ14 VCCQ GND DQ15 DQ16 NC NC GND VCCQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16
A17 NC NC VCCQ GND NC NC DQ8 DQ7 GND VCCQ DQ6 DQ5 GND NC VCC ZZ DQ4 DQ3 VCCQ GND DQ2 DQ1 NC NC GND VCCQ NC NC NC
256K x 16
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable BWE GW OE DQ1-DQ16 MODE VCC GND VCCQ ZZ Synchronous Byte Write Enable Synchronous Global Write Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V Snooze Enable
A2-A17 CLK ADSP ADSC ADV BW1-BW2
CE, CE2, CE2 Synchronous Chip Enable
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/17/01
3
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