|
Details, datasheet, quote on part number:IS61SP6436-4.8I
| |
Datasheet text preview:
IS61SP6436
IS61SP6436
64K x 36 SYNCHRONOUS PIPELINED STATIC RAM
ISSI
JULY 1999
® ISSI
®
FEATURES
· Internal self-timed write cycle · Individual Byte Write Control and Global Write · Clock controlled, registered address, data and control · PentiumTM or linear burst sequence control using MODE input · Three chip enables for simple depth expansion and address pipelining · Common data inputs and data outputs · Power-down control by ZZ input · JEDEC 100-Pin TQFP and PQFP package · Single +3.3V power supply · Two Clock enables and one Clock disable to eliminate multiple bank bus contention. · Control pins mode upon power-up: MODE in interleave burst mode ZZ in normal operation mode These control pins can be connected to GNDQ or VCCQ to alter their power-up state
DESCRIPTION The ISSI IS61SP6436 is a high-speed, low-power synchronous static RAM designed to provide a burstable, highperformance, secondary cache for the i486TM, PentiumTM, 680X0TM, and PowerPCTM microprocessors. It is organized as 65,536 words by 36 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQP1 and DQ1-DQ8, BW2 controls DQP2 and DQ9-DQ16, BW3 controls DQP3 and DQ17-DQ24, BW4 controls DQP4 and DQ25-DQ32, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61SP6436 and controlled by the ADV (burst address advance) input pin. Asynchronous signals include output enable (OE), sleep mode input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the power-down state. When ZZ is pulled LOW (or no connect), the SRAM normally operates after three cycles of the wake-up period. A LOW input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ (or no connect) on MODE pin selects INTERLEAVED Burst.
FAST ACCESS TIME
Symbol t KQ tKC Parameter Clock Access Time Cycle Time Frequency -133 5 7.5 133 -117 5 8.5 117 -5 5 10 100 -6 6 12 83 -7 7 13 75 -8 8 15 66 Unit ns ns MHz
This document contains PRELIMINARY data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1997, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
SR029-1C 08/11/99
1
IS61SP6436
BLOCK DIAGRAM
MODE Q0 A0'
ISSI
®
CLK
CLK
A0
BINARY COUNTER
ADV ADSC ADSP
CE CLR
Q1
A1' A1
64K x 36 MEMORY ARRAY
14 16
A15-A0
16
D
Q
ADDRESS REGISTER
CE
CLK 36 36
GW BWE BW4
DQP4 DQ32-DQ25 BYTE WRITE REGISTERS
CLK
D
Q
BW3
DQP3 Q DQ24-DQ17 BYTE WRITE REGISTERS
CLK
D
BW2
DQP2 DQ16-DQ9 BYTE WRITE REGISTERS
CLK
D
Q
BW1
DQP1 Q DQ8-DQ1 BYTE WRITE REGISTERS
CLK
D
CE
CE2 D Q
4
CE2
ENABLE REGISTER
INPUT REGISTERS
CLK
OUTPUT REGISTERS
CLK OE
36 DATA[36:1]
CE
CLK
D
Q
ENABLE DELAY REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc.
SR029-1C 08/11/99
IS61SP6436
PIN CONFIGURATION
100-Pin TQFP and PQFP (Top View)
GW BWE OE ADSC ADSP ADV
VCC GND CLK CE2
ISSI
®
A6 A7
BW4 BW3 BW2 BW1 CE2
CE
DQP3 DQ17 DQ18 VCCQ GNDQ DQ19 DQ20 DQ21 DQ22 GNDQ VCCQ DQ23 DQ24 VCCQ VCC NC GND DQ25 DQ26 VCCQ GNDQ DQ27 DQ28 DQ29 DQ30 GNDQ VCCQ DQ31 DQ32 DQP4
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A8 A9
DQP2 DQ16 DQ15 VCCQ GNDQ DQ14 DQ13 DQ12 DQ11 GNDQ VCCQ DQ10 DQ9 GND NC VCC ZZ DQ8 DQ7 VCCQ GNDQ DQ6 DQ5 DQ4 DQ3 GNDQ VCCQ DQ2 DQ1 DQP1
PIN DESCRIPTIONS
A0-A15 CLK Address Inputs Clock Processor Address Status Controller Address Status Burst Address Advance Synchronous Byte Write Enable Byte Write Enable Global Write Enable Synchronous Chip Enable Output Enable GNDQ DQ1-DQ32 DQP1-DQP4 ZZ MODE VCC GND VCCQ Data Input/Output Parity Inputs/Outputs Sleep Mode Burst Sequence Mode +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V Isolated Output Buffer Ground
ADSP ADSC ADV BW1-BW4 BWE GW CE, CE2, CE2 OE
Integrated Silicon Solution, Inc.
SR029-1C 08/11/99
MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 NC
3
|
|
