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Part: IS61VPD51236-200TQI
Category:
Memory
-> SRAM
-> Sync. SRAM
Description: 512Kx36
Company: Integrated Silicon Solution Inc.
Datasheet: Download IS61VPD51236-200TQI datasheet File size : 215 kB
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Datasheet text preview:
IS61VPD51232 IS61VPD51236 IS61VPD10018
512K x 32, 512K x 36, 1024K x 18 SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
ISSI
®
ADVANCE INFORMATION SEPTEMBER 2001
FEATURES
· Internal self-timed write cycle · Individual Byte Write Control and Global Write · Clock controlled, registered address, data and control · Linear burst sequence control using MODE input · Three chip enable option for simple depth expansion and address pipelining · Common data inputs and data outputs · JEDEC 100-Pin TQFP and 119-pin PBGA package · Single +2.5V, ±5% operation · Auto Power-down during deselect · Double cycle deselect · Snooze MODE for reduced-power standby · JTAG Boundary Scan for PBGA package
DESCRIPTION T h e I S S I I S 6 1 V P D 5 1 2 3 2 , IS61VPD51236, and
IS61VPD10018 are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61VPD51232 is organized as 524,288 words by 32 bits and the IS61VPD51236 is organized as 524,288 words by 36 bits. The IS61VPD10018 is organized as 1,048,576 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edgetriggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE).input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol t KQ tKC Parameter Clock Access Time Cycle Time Frequency -200 3.1 5 200 -166 3.5 6 166 Units ns ns MHz
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 09/25/01 Rev. 00B
1
IS61VPD51232 IS61VPD51236 IS61VPD10018
BLOCK DIAGRAM
MODE Q0 A0'
ISSI
®
CLK
CLK
A0
BINARY COUNTER
ADV ADSC ADSP CE CLR Q1 A1' A1
512Kx32; 512Kx36; 1024Kx18 MEMORY ARRAY
17/18 19/20 Q
19/20 A D
ADDRESS REGISTER
CE CLK 32, 36, or 18 32, 36, or 18
GW BWE BWd (x32/x36)
DQd BYTE WRITE REGISTERS
CLK
D
Q
BWc (x32/x36)
D DQc Q BYTE WRITE REGISTERS CLK
BWb (x32/x36/x18)
DQb BYTE WRITE REGISTERS
CLK
D
Q
BWa (x32/x36/x18)
D DQa Q BYTE WRITE REGISTERS CLK
CE CE2 CE2 D Q
4
ENABLE REGISTER
CE CLK
INPUT REGISTERS
CLK
OUTPUT REGISTERS
CLK OE
32, 36, or 18 DQa - DQd
D
Q
ENABLE DELAY REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00B 09/25/01
IS61VPD51232 IS61VPD51236 IS61VPD10018
PIN CONFIGURATION
100-Pin TQFP
A A CE CE2 BWd BWc BWb BWa CE 2 VCC GND CLK GW BWE OE A DS C ADSP ADV A A
ISSI
®
NC DQc DQc VCCQ GND DQc DQc DQc DQc GND VCCQ DQc DQc NC VCC NC GND DQd DQd VCCQ GND DQd DQd DQd DQd GND VCCQ DQd DQd NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC DQb DQb VCCQ GND DQb DQb DQb DQb GND VCCQ DQb DQb GND NC VCC ZZ DQa DQa VCCQ GND DQa DQa DQa DQa GND VCCQ DQa DQa NC
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Controller Address Status Synchronous Processor Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable Synchronous Clock DQa-DQd GND GW MODE OE VCC VCCQ ZZ Synchronous Data Input/Output Ground Synchronous Global Write Enable Burst Sequence Mode Selection Output Enable +2.5V Power Supply Isolated Output Buffer Supply: +2.5V Snooze Enable
A ADSC ADSP ADV BWa-BWd BWE CLK
CE, CE2, CE2 Synchronous Chip Enable
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION 09/25/01 Rev. 00B
MODE A A A A A1 A0 NC NC GND VCC A A A A A A A A A
512K x 32
3
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