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Details, datasheet, quote on part number:IS71V16F32BS08
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| Part: | IS71V16F32BS08 |
| Category: | Memory => Multi Chip Memory => Flash + SRAM |
| Description: | 3.0 Volt-only Flash & SRAM Combo With Stacked Multi-chip Package (MCP) 32 Mbit Simultaneous Operation Flash Memory And 8 Mbit Static RAM |
| Company: | Integrated Silicon Solution Inc. |
| Datasheet: | Download IS71V16F32BS08 datasheet File size : 337 kB |
| Request For quote: | Find where to buy IS71V16F32BS08
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Datasheet text preview:
IS71V08F32XS08 IS71V16F32XS08
3.0 Volt-Only Flash & SRAM COMBO with Stacked Multi-Chip Package (MCP) -- 32 Mbit Simultaneous Operation Flash Memory and 8 Mbit Static RAM MCP FEATURES
· Power supply voltage 2.7V to 3.3V · High performance:
Flash: 70ns maximum access time SRAM: 70ns maximum access time
ISSI
· Ready-Busy output (RY/BY): Detection
of program or erase cycle completion
®
PRELIMINARY INFORMATION MAY 2002
· Package:
73-ball BGA - 32 Mbit Flash/8 Mbit SRAM
· Over 100,000 write/erase cycles · Low supply voltage (Vccf 2.5V) inhibits writes · WP/ACC input pin:
If VIL, allows protection of boot sectors If VIH, allows removal of boot sector protection If Vacc, program time is reduced by 40%
· Operating Temperature: -40C to +85C
· Boot sector: Top or Bottom
FLASH FEATURES · Power Dissipation:
Read Current at 1 Mhz: 7 mA maximum Read Current at 5 Mhz: 18 mA maximum Sleep Mode: 5 µA maximum
SRAM FEATURES (8 Mb density) · Power Dissipation:
Operating: 25 mA maximum Standby: 15 µA maximum Chip Selects: CE1s, CE2s Power down feature using CE1s, or CE2s or LBs & UBs Data retention supply voltage: 1.0 to 3.3 volt Byte data control: LBs (DQ0DQ7), UBs (DQ8DQ15) -- on x16 version
· Simultaneous Read and Write Operations:
Zero latency between read and write operations; Data can be programmed or erased in one bank while data is simultaneously being read from the other bank
· Low-Power Mode:
A period of no activity causes flash to enter a low-power state
· · · ·
· Erase Suspend/Resume:
Suspends of erase activity to allow a read in the same bank
GENERAL DESCRIPTION
The flash and SRAM MCP is available in 32 Mbit Flash/8 Mbit SRAM having a data bus of either x8 or x16. The 32 Mbit flash is composed of 2,097,152 words of 16 bits or 4,194,304 bytes of 8 bits. Data lines DQ0-DQ7 handle the x8 format, while lines DQ0-DQ15 handle the x16 format. The package uses a 3.0V power supply for all operations. No other source is required for program and erase operations. The flash can be programmed in system using this 3.0V supply, or can be programmed in a standard EPROM programmer. The 32 Mbit flash/8 Mbit SRAM is offered in a 73-pin BGA package. The flash is compatible with the JEDEC Flash command set standard . The flash access time is 70 ns and the SRAM access time is 70ns. The Flash architecture is composed of two banks which allows simultaneous operation on each. Optimized performance can be achieved by first initializing a program or erase function in one bank, then immediately starting a read from the other bank. Both operations would then be operating simultaneously, with zero latency.
· Sector Erase Architecture:
8 words of 4k size and 63 words of 32K size (32 Mbit) Any combination of sectors, or the entire flash can be simultaneously erased
· Erase Algorithms:
Automatically preprograms/erases the flash memory entirely, or by sector
· Program Algorithms:
Automatically writes and verifies data at specified address
· Hidden ROM Region:
64KB with a Factory-serialized secure electronic serial number (ESN), which is accessible through a command sequence
· Data Polling and Toggle Bit:
Allow for detection of program or erase cycle completion
ISSI reserves the right to make changes this specification herein and it products at any time without notice. ISSI assumes no responsibility or liability arising out of the application or use of any information, product or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. © Copyright 2002, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B 05/23/02
1
IS71V08F32XS08, IS71V16F32XS08
ISSI
VCCf GND RY/BY
®
MCP BLOCK DIAGRAM
A0-A20 A-1 WP/ACC RESET C Ef I/Of
32Mb Flash Memory DQ0-DQ15/A-1
VCCS GND A0-A18 SA LBs U Bs WE OE CE1s CE2s DQ0-DQ15 8Mb Static RAM
LOGIC SYMBOL
22 A0-A20, A-1 SA CEf CE1s CE2s OE WE WP/ACC RESET UBs LBs I/Of DQ0-DQ15 16 or 8 RY/BY
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Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B 05/23/02
IS71V08F32XS08, IS71V16F32XS08
ISSI
OE BYTE
®
FLASH MEMORY BLOCK DIAGRAM
VCC GND A0-A20 Upper Bank Address Y-Decoder RY/BY A0-A20 RESET WE CE BYTE WP/ACC DQ0-DQ15 A0-A20 Lower Bank Latches and Control Logic STATE CONTROL & COMMAND REGISTER Control DQ0-DQ15 A0-A20 X-Decoder DQ0-DQ15 DQ0-DQ15 Upper Bank Latches and Control Logic
Status
A0-A20
Lower Bank Address
Y-Decoder
X-Decoder OE BYTE
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B 05/23/02
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