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Details, datasheet, quote on part number:28F016SV-120
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Datasheet text preview:
Intel£ Advanced Boot Block Flash M emory (B3)
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet
Product Features
· Flexible SmartVoltage Technology
-- 2.7 V3.6 V Read/Program/Erase -- 12 V VPP Fast Production Programming
· Intel® Flash Data Integrator Software
-- Flash Memory Manager -- System Interrupt Manager -- Supports Parameter Storage, Streaming Data (e.g., Voice)
· 1.65 V2.5 V or 2.7 V3.6 V I/O Option
-- Reduces Overall System Power
· High Performance
-- 2.7 V3.6 V: 70 ns Max Access Time
· Extended Cycling Capability
-- Minimum 100,000 Block Erase Cycles G uaranteed
· Optimized Block Sizes
-- Eight 8-KB Blocks for Data,Top or Bottom Locations -- Up to One Hundred Twenty-Seven 64KB Blocks for Code
· Automatic Power Savings Feature
-- Typical ICCS after Bus Inactivity
· Standard Surface Mount Packaging
-- 48-Ball CSP Packages -- 40- and 48-Lead TSOP Packages
· Block Locking
-- VCC-Level Control through WP#
· c ensity and Footprint Upgradeable for D
ommon package -- 8-, 16-, 32- and 64-Mbit Densities e c hnology -- 16 and 32-Mbit Densities
· Low Power Consumption
-- 9 mA Typical Read Current
· Absolute Hardware-Protection
-- VPP = GND Option -- VCC Lockout Voltage
· ETOXTM VIII (0.13 µm) Flash T · ETOXTM VII (0.18 µm) Flash Technology
-- 16-, 32- and 64-Mbit Densities
· Extended Temperature Operation
-- 40 °C to +85 °C
· Automated Program and Block Erase
-- Status Registers
· ETOX TM VI (0.25µm) Flash Technology
-- 8-, 16-, and 32-Mbit Densities
· The x8 option not recommended for new d
esigns
The Intel® Advanced Boot Block Flash Memory (B3) device, manufactured on Intel's latest 0.13 µm and 0.18 µm technologies, represents a feature-rich solution at overall lower system cost. o he B3 device in x16 will be available in 48-lead TSOP and 48-ball CSP packages. The x8 T A tion of this product family is available only in 40-lead TSOP and 48-ball µBGA* packages. p dditional information on this product family can be obtained by accessing Intel's website at: http://www.intel.com/design/flash.
Notice: This specification is subject to change without notice. Verify with your local Intel sales o ffice that you have the latest datasheet before finalizing a design.
Order Number: 290580-017 May 2003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY E I STOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN A TEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS N RNY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES ELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://developer.intel.com/design/flash. Copyright © Intel Corporation 2003. *Other names and brands may be claimed as the property of others.
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D at as h ee t
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Contents
1. 0 2. 0 Introduction ......... 7
1.1 2.1 2.2 Product Overview ........ 8 Package Pinouts ......... 9 Block Organization .... 13 2.2.1 Parameter Blocks .. 14 2.2.2 Main Blocks ........... 14 Bus Operation ........... 14 3.1.1 Read ............. 15 3.1.2 Output Disable.......15 3.1.3 Standby ........ 15 3.1.4 Deep Power-Down / Reset............15 3.1.5 Write ............. 16 Modes of Operation ............ 16 3.2.1 Read Array ............ 16 3.2.2 Read Identifier ....... 17 3.2.3 Read Status Register ........... 18 3.2.3.1 Clearing the Status Register ..... 18 3.2.4 Program Mode.......19 3.2.4.1 Suspending and Resuming Program ....... 19 3.2.5 Erase Mode ........... 19 3.2.5.1 Suspending and Resuming Erase ............ 20 Block Locking ............ 21 3.3.1 WP# = VIL for Block Locking ......... 21 3.3.2 WP# = VIH for Block Unlocking ..... 22 VPP Program and Erase Voltages ..... 22 3.4.1 VPP = VIL for Complete Protection ......... 22 Power Consumption ........... 22 3.5.1 Active Power ......... 23 3.5.2 Automatic Power Savings (APS) ... 23 3.5.3 Standby Power ...... 23 3.5.4 Deep Power-Down Mode ..... 23 Power and Reset Considerations......23 3.6.1 Power-Up/Down Characteristics ... 23 3.6.2 RP# Connected to System Reset .. 24 3.6.3 VCC, VPP and RP# Transitions ...... 24 Power Supply Decoupling .. 24 Absolute Maximum Ratings ......... 25 Operating Conditions..........26 DC Current Characteristics ......... 26 DC Voltage Characteristics ......... 29
Product Description ........ 9
3. 0
Principles of Operation ......... 14
3.1
3.2
3.3
3.4 3.5
3.6
3.7
4. 0
Thermal and DC Characteristics......25
4.1 4.2 4.3 4.4
Datasheet
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
5.0
AC Characteristics......... 30
5.1 5.2 5.3 5.4 5.5 5.6 AC Read Characteristics .... 30 AC Write Characteristics .... 34 Erase and Program Timings ....... 38 Reset Specifications........... 39 AC I/O Test Conditions ...... 40 Device Capacitance ........... 40
6.0 7.0 8.0
Reset Operations ........... 41 Ordering Information .... 42 Additional Information .......... 44 Write State Machine Current/Next States ....... 45 Architecture Block Diagram ......... 46 Word-Wide Memory Map Diagrams.... 47 Byte-Wide Memory Map Diagrams ..... 53 Program and Erase Flowcharts ........... 56 Mechanical Specifications ...... 60
Appendix A Appendix B Appendix C Appendix D Appendix E Appendix F
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D at as h ee t
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Revision History
Number -001 Original version Section 3.4, VPP Program and Erase Voltages, added Updated Figure 9: Automated Block Erase Flowchart Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table) Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes) IPPR maximum specification change from ±25 µA to ±50 µA Program and Erase Suspend Latency specification change Updated Appendix A: Ordering Information (included 8 M and 4 M information) Updated Figure, Appendix D: Architecture Block Diagram (Block info. in words not bytes) Minor wording changes Combined byte-wide specification (previously 290605) with this document Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V) Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4) Improved several DC characteristics (Section 4.4) Improved several AC characteristics (Sections 4.5 and 4.6) Combined 2.7 V and 1.8 V DC characteristics (Section 4.4) Added 5 V VPP read specification (Section 3.4) Removed 120 ns and 150 ns speed offerings Moved Ordering Information from Appendix to Section 6.0; updated information Moved Additional Information from Appendix to Section 7.0 Updated figure Appendix B, Access Time vs. Capacitive Load Updated figure Appendix C, Architecture Block Diagram Moved Program and Erase Flowcharts to Appendix E Updated Program Flowchart Updated Program Suspend/Resume Flowchart Minor text edits throughout Added 32-Mbit density Added 98H as a reserved command (Table 4) A1A20 = 0 when in read identifier mode (Section 3.2.2) Status register clarification for SR3 (Table 7) VCC and VCCQ absolute maximum specification = 3.7 V (Section 4.1) Combined IPPW and ICCW into one specification (Section 4.4) Combined IPPE and ICCE into one specification (Section 4.4) Max Parameter Block Erase Time (tWHQV2/tEHQV2) reduced to 4 sec (Section 4.7) Max Main Block Erase Time (tWHQV3/tEHQV3) reduced to 5 sec (Section 4.7) Erase suspend time @ 12 V (tWHRH2/tEHRH2) changed to 5 µs typical and 20 µs maximum (Section 4.7) Ordering Information updated (Section 6.0) Write State Machine Current/Next States Table updated (Appendix A) Program Suspend/Resume Flowchart updated (Appendix F) Erase Suspend/Resume Flowchart updated (Appendix F) Text clarifications throughout µBGA package diagrams corrected (Figures 3 and 4) IPPD test conditions corrected (Section 4.4) 32-Mbit ordering information corrected (Section 6) µBGA package top side mark information added (Section 6) VIH and VILSpecification change (Section 4.4) ICCS test conditions clarification (Section 4.4) Added Command Sequence Error Note (Table 7) Data sheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash M emory Family. Added device ID information for 4-Mbit x8 device Removed 32-Mbit x8 to reflect product offerings Minor text changes Corrected RP# pin description in Table 2, 3 Volt Advanced Boot Block Pin Descriptions Corrected typographical error fixed in Ordering Information Description
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Datasheet
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