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Details, datasheet, quote on part number:430HX
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| Part: | 430HX |
| Category: | Interface and Interconnect => Controllers => System Controllers |
| Description: | Pciset 82439hx System Controller (txc) |
| Company: | Intel Corporation |
| Datasheet: | Download 430HX datasheet File size : 581 kB |
| Request For quote: | Find where to buy 430HX
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Datasheet text preview:
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INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC)
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Optional Error Checking and Correction (ECC)
Superior DRAM Data Integrity Single Bit Error Correction, Multi-Bit Error Detection plus Nibble Failure Detection ECC Code Single and Multi-Bit Error Reporting Virtual Swapable Bank Support (i.e., can swap out problem banks) Merging Write Buffer Eliminates Most Partial Writes Cycles
Supports All 3V Pentium ® Processors Dual Processor Support PCI 2.1 Compliant Integrated Second-Level Cache Controller
Direct Mapped Organization Write-Back Cache Policy Cacheless, 256 KB, and 512 KB Pipelined Burst SRAMs Cache Hit Read/Write Cycle Timings at 3-1-1-1 Back-to-Back Read Cycles at 3-1-1-1-1-1-1-1 Integrated Tag/Valid Status Bits for Cost Savings and Performance Optional 512-MB DRAM Cacheability Limit Supports 5V SRAMs for Tag Address
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Fully Synchronous, Minimum Latency 25/30/33 MHz PCI Bus Interface
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Integrated DRAM controller
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4-MB to 512-MB Main Memory 64-Mb DRAM Technology Support 8-QWord Deep Merging DRAM Write Buffer Enhanced EDO/Hyper Page Mode DRAM; 4-2-2-2 Reads and x-2-2-2 Writes at 60 MHz; 5-2-2-2 Reads and x-2-2-2 Writes at 66 MHz 8 RAS Lines Integrated Programmable-Strength Memory Address Buffers CAS-Before-RAS Refresh
Zero Wait State CPU-to-PCI Write Timings (no IRDY stall) for Superior Graphics Performance Enhanced CPU-to-PCI Read Latencies for Superior Graphics/PIO Performance 21-DWord PCI-DRAM Post Buffer 22-DWord PCI-to-DRAM Read Prefetch Buffer Write-Back Merging for PCI to DRAM Writes Write-Back Forwarding for PCI to DRAM Reads Pipelined Snoop Ahead Multi-Transaction Timer to Support Multiple Short PCI Transactions Within the Same PCI Arbitration Cycle
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Supports the Universal Serial Bus (USB) Supported Kits
82439HX ISA Kit (TXC, PIIX3) 82439HX ISA/DP Kit (TXC, PIIX3, IOAPIC)
Optional Parity Single 324-Pin BGA Package
The Intel 430HX PCIset consists of the 82439HX System Controller (TXC) and the 82371SB PCI I/O IDE Xcelerator (PIIX3). The TXC is a single-chip host-to-PCI bridge and provides the second level cache control and DRAM control functions. The second level (L2) cache controller supports a write-back cache policy for cache sizes of 256 Kbytes and 512 Kbytes. Cacheless designs are also supported. The cache memory is implemented with synchronous pipelined burst SRAMs. An external Tag RAM is used for the address tag and an internal Tag RAM for the cache line status bits. The TXC provides a 64/72-bit data path to main memory and memory sizes up to 512 Mbytes. The DRAM controller provides eight rows and optional DRAM Error detection/correction or parity. The TXC's optimized PCI interface allows the CPU to sustain the highest possible bandwidth to the graphics frame buffer at all frequencies. Using the snoop ahead feature, The TXC allows PCI masters to achieve full PCI bandwidth. For increased system performance, the TXC contains read prefetch and posted write buffers.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by the sale of Intel products. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoev er, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life sav ing, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The Intel 430HX PCIset may contain design defects or errors known as errata. Current characterized errata are available on request. *Third-party brands and names are the property of their respective owners.
© INTEL CORPORATION 1997
April 1997
Order Number: 290551-002
82439HX (TXC)
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Ho st Interfa ce PCI Interface AD[3 1:0] C/BE[3:0 ]# FRAME# TRDY# IRDY# STOP# LOCK# DEVSEL# PAR REQ[3 :0 ]# GNT [3:0 ]# PHLDA# PHLD# SERR# MD [63 :0] MP D[7:0] RAS[7 :0]# CAS [7:0]# MA [11 :2] MAA[1:0] MAB[1:0] MWE# HCLKIN PCLK IN R S T# TEST#
HD[6 3:0] A[31 :3]
BE[7 :0]# ADS# D/C# M/IO# W/R# BRDY# EADS# HITM# BOFF# AHOLD NA# KEN#/INV CACHE# HLOCK# SMIACT#
CCS# TWE# COE# GWE# CADS# CADV# TIO[7:0] TIO[10:8] BWE
DR AM Interfa ce C ac he Interfa ce
Clocks, Reset, and Test
055101
82439HX TXC Simplified Block Diagram
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82439HX (TXC)
CONTENTS
PAGE
REVISION HISTORY..... 4 1.0. ARCHITECTURE OVERVIEW........ 5 2.0. SIGNAL DESCRIPTION ........ 7 2.1. Host Interface...... 7 2.2. DRAM Interface .. 8 2.3. Secondary Cache Interface ......... 9 2.4. PCI Interface ..... 10 2.5. Clock, Reset, and Test ..... 11 3.0. REGISTER DESCRIPTION .......... 12 3.1. I/O Control Registers........ 12 3.1.1. CONFADDCONFIGURATION ADDRESS REGISTER ... 12 3.1.2. CONFDATACONFIGURATION DATA REGISTER ......... 13 3.2. PCI Configuration Space Mapped Registers ..... 14 3.2.1. PCI CONFIGURATION ACCESS ...... 14 3.2.2. VIDVENDOR IDENTIFICATION REGISTER ......... 15 3.2.3. DIDDEVICE IDENTIFICATION REGISTER ........... 16 3.2.4. PCICMDPCI COMMAND REGISTER ..... 16 3.2.5. PCISTSPCI STATUS REGISTER........... 17 3.2.6. RIDREVISION IDENTIFICATION REGISTER ....... 17 3.2.7. CLASSCCLASS CODE REGISTER ....... 18 3.2.8. MLTMASTER LATENCY TIMER REGISTER ........ 18 3.2.9. HEADTHEADER TYPE REGISTER ....... 19 3.2.10. BISTBIST REGISTER... 19 3.2.11. ACONARBITRATION CONTROL ......... 19 3.2.12. PCONPCI CONTROL ... 20 3.2.13. CCCACHE CONTROL REGISTER....... 21 3.2.14. DRAMECDRAM EXTENDED CONTROL REGISTER .. 22 3.2.15. DRAMCDRAM CONTROL REGISTER .......... 23 3.2.16. DRAMTDRAM TIMING REGISTER ...... 23 3.2.17. PAMPROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM[6:0]) ... 25 3.2.18. DRBDRAM ROW BOUNDARY REGISTERS....... 27 3.2.19. DRTDRAM ROW TYPE REGISTER ..... 29 3.2.20. SMRAMSYSTEM MANAGEMENT RAM CONTROL REGISTER ......... 29 3.2.21. ERRCMDERROR COMMAND REGISTER.......... 31 3.2.22. ERRSTSERROR STATUS REGISTER ......... 32 3.2.23. ERRSYN -- ERROR SYNDROME REGISTER....... 33
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82439HX (TXC)
4.0. FUNCTIONAL DESCRIPTION ..... 34 4.1. Host Interface.... 34 4.2. PCI Interface ..... 34 4.3. Secondary Cache Interface ....... 34 4.3.1. CLOCK LATENCIES .......... 35 4.3.2. SNOOP CYCLES ...... 36 4.3.3. CACHE ORGANIZATION... 36 4.3.4. DRAM CACHE .......... 37 4.4. DRAM Interface ...... 38 4.4.1. DRAM ORGANIZATION..... 38 4.4.2. DRAM ADDRESS TRANSLATION.... 42 4.4.3. DRAM TYPES ........... 43 4.4.4. DRAM PERFORMANCE .... 44 4.4.5. DRAM REFRESH...... 46 4.4.6. SYSTEM MANAGEMENT RAM ........ 47 4.4.7. DATA INTEGRITY SUPPORT........... 47 4.4.7.1. Parity ... 47 4.4.7.2. Error Detection and correction .... 47 4.5. PCI Bus Arbitration........... 49 4.5.1. CPU POLICIES ......... 50 4.6. Clock Generation and Distribution ............ 50 4.6.1. RESET SEQUENCING ...... 50 5.0. PINOUT AND PACKAGE INFORMATION ........... 51 5.1. TXC Pinout Information .... 51 5.2. TXC Package Information ......... 56 6.0. TESTABILITY....... 59 6.1. NAND Tree Mode............. 59 6.1.1. OVERVIEW ...... 59 6.1.2. NAND CHAIN MODE ......... 60 6.2. ID Code Test Mode .......... 65
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REVISION HISTORY
Revision Date July 1996 April 1997 -001 -002 Version Description Initial Release Included information from Specification Update
The Intel 430HX PCIset device may contain design defects or errors known as errata. Characterized errata that may cause the 430HX's behavior to deviate from published specifications are documented in the "Intel 430HX PCIset: 82439HX (TXC) Specification Update" (Order number 297652).
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1.0.
Data Flow
82439HX (TXC)
ARCHITECTURE OVERVIEW
The TXC interfaces with the Pentium® processor host bus, a dedicated memory data bus, and the PCI bus (Figure 1). The TXC connects directly to the Pentium processor 3V host bus, directly to 5V or 3V DRAMs, and directly to the 5V PCI bus. The Intel 430HX PCIset consists of the 82439HX TXC and the PCI IDE/ISA Xcellerator (PIIX3) components. PIIX3 provides the PCI-to-ISA bridge functions along with other features such as a fast IDE interface, Plug-n-Play port, APIC interface, Universal Serial Bus (USB) and PCI 2.1 Compliance operation.
Processor cycles are sent directly to the second level cache with control for the second level cache provided by the TXC. All other processor cycles are sent to their destination (DRAM, PCI or internal TXC configuration space) via the TXC. PCI Master cycles are sent to main memory through the TXC. The TXC performs snoop or inquire cycles using the host bus.
Pentium® Processor Host Bus 3.3V Control Address Data Second Level Cache Cache (SRAM) Cntl Tag Cntl TIO[7:0] TIO[10:8] TXC Addr Data ECC Cntl Main Memory (DRAM)
Tag
PCI Bus Control Address/Data
Hard CD ROM Disk
Fast IDE PIIX3
USB 1
USB 2 ISA Device(s)
PCI Device(s)
Universal Serial Bus
ISA Bus
055102
Figure 1. TXC System Block Diagram
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