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Part: 440GXAGP
Category:
Interface and Interconnect
Description: 82443gx Host Bridge/controller
Company: Intel Corporation
Datasheet: Download 440GXAGP datasheet File size : 158 kB
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Intel® 440GX AGPset: 82443GX Host Bridge/Controller
Datasheet
June 1998
Order Number: 290638-001
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. The 82443GX chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available upon request. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by: calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1997-1998 *Third-par ty brands and names are the property of their respective owners.
82443GX Host Bridge Datasheet
Intel 82443GX Features
· Processor/System bus support
-- Optimized for Pentium® II and Pentium® II XeonTM processors at 100 MHz system bus frequency -- Supports full symmetric Multiprocessor (SMP) Protocol for up to two processors; I/O APIC related buffer management support (WSC# signal) -- In-order transaction and dynamic deferred transaction support -- Supports GTL+ and AGTL+ bus driver technology (gated GTL+ receivers for reduced power) Integrated DRAM controller -- 16 MB to 2 GB -- Supports up to 4 double-sided DIMMs (8 rows memory) -- 64-bit data interface with ECC support (SDRAM only) -- Unbuffered and Registered SDRAM (Synchronous) Support (x-1-1-1 access @ 100 MHz) -- Enhanced SDRAM Open Page Architecture Support for 16-, 64-, 128-, and 256-Mbit* DRAM devices with 2k, 4k and 8k page sizes -- PCI Rev. 2.1, 3.3V and 5V, 33MHz interface compliant -- PCI Parity Generation Support -- Data streaming support from PCI to DRAM -- Delayed Transaction support for PCI-DRAM Reads -- Supports concurrent CPU, AGP and PCI transactions to main memory
· AGP interface
-- Supports single AGP compliant device (AGP-66/133 3.3V device) -- AGP Specification Rev 1.0 compliant -- AGP-data/transaction flow optimized arbitration mechanism -- AGP side-band interface for efficient request pipelining without interfering with the data streams -- AGP-specific data buffering -- Supports concurrent CPU, AGP and PCI transactions to main memory -- AGP high-priority transactions ("expedite") support Power management functions -- Stop Clock Grant and Halt special cycle translation (host to PCI Bus) -- "Deep Green" Desktop support for system suspend/resume (i.e., DRAM and power-on suspend) -- SDRAM self-refresh power down support in suspend mode -- Independent, internal dynamic clock gating reduces average power dissipation -- Static STOP CLOCK support -- Power-on Suspend mode -- Suspend to DRAM -- ACPI compliant power management Packaging/Voltage -- 492 Pin BGA -- 3.3V core & mixed 3.3V & GTL I/O Supporting I/O Bridge -- System Management Bus (SMB) with support for DIMM Serial Presence Detect (SPD) -- PCI-ISA Bridge (PIIX4E) -- Power Management Support -- 3.3V core and mixed 5V, 3.3V I/O and interface to the 2.5V CPU signals via open-drain output buffers
·
·
· PCI bus interface · ·
The Intel® 440GX AGPset is intended for the Pentium® II processor and Pentium® II XeonTM processor platforms. The 82443GX Host Bridge provides a Host-to-PCI bridge, optimized DRAM controller and data path, and an Accelerated Graphic Port (AGP) interface. AGP is a high performance, component level interconnect targeted at 3D graphics applications and is based on a set of performance enhancements to PCI. The I/O subsystem portion of the Intel® 440GX AGPset platform is based on the 82371EB (PIIX4E), a highly integrated version of the Intel's PCI-ISA bridge family.
* Proper operation of the 82443GX AGPset with 256-Mbit SDRAM devices has not yet been verified. Intel's current plans are to validate this feature in the second half of 1998 when 256-Mbit SDRAM devices are available. The Intel 82443GX may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Current characterized errata are available on request.
82443GX Host Bridge Datasheet
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Intel 82443GX Simplified Block Diagram
A[31:3]# ADS# BPRI# BNR# CPURST# DBSY# DEFER# HD[63:0]# HIT# HITM# HLOCK# HREQ[4:0]# HTRDY# DRDY# RS[2:0]# CSA[7:0]# CSB[7:0]# DQMA[7:0] DQMB[5,1] GCKE SRAS[B,A]# FENA SCAS[B,A]# MAA[14:0] MAB[14,13,12#,11#,10,9#:0 #] WEA# WEB# MD[63:0] MECC[7:0] AD[31:0] C/BE[3:0]# FRAME# TRDY# IRDY# DEVSEL# PAR SERR# PLOCK# STOP# PHOLD# PHLDA# WSC# PREQ0# PREQ[4:1]# PGNT0# PGNT[4:1]# GAD[31:0] GC/BE[3:0]# GFRAME# GIRDY# GTRDY# GSTOP# GDEVSEL# GREQ# GGNT# GPAR PIPE# SBA[7:0] RBF# STOP# ST[2:0] ADSTB_A ADSTB_B SBSTB
Host Interface
PCI Bus Interface (PCI #0)
DRAM Interface
AGP Interface
HCLKIN PCLKIN GTLREF[B:A] AGPREF VTT[B:A] REF5V PCIRST# CRESET# BREQ0# TESTIN# GCLKO GCLKIN DCLKO DCLKWR
Clocks, Reset, Test, and Misc.
Power Mgnt
CLKRUN# SUSTAT# GXPWROK
GX_BLK.VSD
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82443GX Host Bridge Datasheet
Contents
1 2 Architectural Overview ..... 1-1 Signal Description ............ 2-1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3 3.1 Host Interface Signals..2-1 DRAM Interface ........... 2-3 PCI Interface (Primary) ......... 2-4 Primary PCI Sideband Interface .......... 2-6 AGP Interface Signals..2-6 Clocks, Reset, and Miscellaneous ....... 2-8 Power-Up/Reset Strap Options............2-9 I/O Mapped Registers .. 3-2 3.1.1 CONFADD--Configuration Address Register..........3-2 3.1.2 CONFDATA--Configuration Data Register .... 3-3 3.1.3 PM2_CTL--ACPI Power Control 2 Control Register ..... 3-4 PCI Configuration Space Access.........3-4 3.2.1 Configuration Space Mechanism Overview .... 3-5 3.2.2 Routing the Configuration Accesses to PCI or AGP ...... 3-5 3.2.3 PCI Bus Configuration Mechanism Overview .......... 3-6 3.2.3.1 Type 0 Access ........... 3-6 3.2.3.2 Type 1 Access ........... 3-6 3.2.4 AGP Bus Configuration Mechanism Overview ........ 3-6 3.2.5 Mapping of Configuration Cycles on AGP ...... 3-7 Host-to-PCI Bridge Registers (Device 0) ...... 3-8 3.3.1 VID--Vendor Identification Register (Device 0).....3-10 3.3.2 DID--Device Identification Register (Device 0) ..... 3-10 3.3.3 PCICMD--PCI Command Register (Device 0) ...... 3-11 3.3.4 PCISTS--PCI Status Register (Device 0) .... 3-12 3.3.5 RID--Revision Identification Register (Device 0) .. 3-13 3.3.6 SUBC--Sub-Class Code Register (Device 0) ....... 3-13 3.3.7 BCC--Base Class Code Register (Device 0) ........ 3-13 3.3.8 MLT--Master Latency Timer Register (Device 0)..3-14 3.3.9 HDR--Header Type Register (Device 0) ...... 3-14 3.3.10 APBASE--Aperture Base Configuration Register (Device 0)........3-14 3.3.11 SVID--Subsystem Vendor Identification Register (Device 0)........3-15 3.3.12 SID--Subsystem Identification Register (Device 0).....3-16 3.3.13 CAPPTR--Capabilities Pointer Register (Device 0) .... 3-16 3.3.14 NBXCFG--NBX Configuration Register (Device 0) ..... 3-16 3.3.15 DRAMC--DRAM Control Register (Device 0) ....... 3-19 3.3.16 PAM[6:0]--Programmable Attribute Map Registers (Device 0)......3-20 3.3.17 DRB[0:7]--DRAM Row Boundary Registers (Device 0) ....... 3-22 3.3.18 FDHC--Fixed DRAM Hole Control Register (Device 0) ....... 3-24 3.3.19 MBSC--Memory Buffer Strength Control Register (Device 0)......3-24 3.3.20 SMRAM--System Management RAM Control Register (Device 0)......3-28
Register Description.........3-1
3.2
3.3
82443GX Host Bridge Datasheet
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