|Category||Interface and Interconnect|
|Description||82443gx Host Bridge/controller|
|Datasheet||Download 440GXAGP datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. The 82443GX chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available upon request. is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by: calling or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1997-1998 *Third-party brands and names are the property of their respective owners.
Optimized for Pentium® II and Pentium® II XeonTM processors at 100 MHz system bus frequency Supports full symmetric Multiprocessor (SMP) Protocol for up to two processors; I/O APIC related buffer management support (WSC# signal) In-order transaction and dynamic deferred transaction support Supports GTL+ and AGTL+ bus driver technology (gated GTL+ receivers for reduced power) Integrated DRAM controller 2 GB Supports to 4 double-sided DIMMs (8 rows memory) 64-bit data interface with ECC support (SDRAM only) Unbuffered and Registered SDRAM (Synchronous) Support (x-1-1-1 access @ 100 MHz) Enhanced SDRAM Open Page Architecture Support for 64-, 128-, and 256-Mbit* DRAM devices with 2k, 4k and 8k page sizes PCI Rev. 2.1, 3.3V and 5V, 33MHz interface compliant PCI Parity Generation Support Data streaming support from PCI to DRAM Delayed Transaction support for PCI-DRAM Reads Supports concurrent CPU, AGP and PCI transactions to main memory
Supports single AGP compliant device (AGP-66/133 3.3V device) AGP Specification Rev 1.0 compliant AGP-data/transaction flow optimized arbitration mechanism AGP side-band interface for efficient request pipelining without interfering with the data streams AGP-specific data buffering Supports concurrent CPU, AGP and PCI transactions to main memory AGP high-priority transactions ("expedite") support Power management functions Stop Clock Grant and Halt special cycle translation (host to PCI Bus) "Deep Green" Desktop support for system suspend/resume (i.e., DRAM and power-on suspend) SDRAM self-refresh power down support in suspend mode Independent, internal dynamic clock gating reduces average power dissipation Static STOP CLOCK support Power-on Suspend mode Suspend to DRAM ACPI compliant power management Packaging/Voltage 492 Pin BGA 3.3V core & mixed 3.3V & GTL I/O Supporting I/O Bridge System Management Bus (SMB) with support for DIMM Serial Presence Detect (SPD) PCI-ISA Bridge (PIIX4E) Power Management Support 3.3V core and mixed 5V, 3.3V I/O and interface to the 2.5V CPU signals via open-drain output buffers
The Intel® 440GX AGPset is intended for the Pentium® II processor and Pentium® II XeonTM processor platforms. The 82443GX Host Bridge provides a Host-to-PCI bridge, optimized DRAM controller and data path, and an Accelerated Graphic Port (AGP) interface. AGP is a high performance, component level interconnect targeted at 3D graphics applications and is based on a set of performance enhancements to PCI. The I/O subsystem portion of the Intel® 440GX AGPset platform is based on the (PIIX4E), a highly integrated version of the Intel's PCI-ISA bridge family.
* Proper operation of the 82443GX AGPset with 256-Mbit SDRAM devices has not yet been verified. Intel's current plans are to validate this feature in the second half of 1998 when 256-Mbit SDRAM devices are available. The Intel 82443GX may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Current characterized errata are available on request.
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