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Details, datasheet, quote on part number:440LX
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| Part: | 440LX |
| Category: | Interface and Interconnect => Chipsets |
| Description: | 440LX AGPset: 82443LX Pci Agp Controller (PAC) |
| Company: | Intel Corporation |
| Datasheet: | Download 440LX datasheet File size : 1067 kB |
| Request For quote: | Find where to buy 440LX
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Datasheet text preview:
82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
Supported Kits for both Pentium and ® Pentium II Microprocessors 82430TX ISA Kit 82440LX ISA/DP Kit Multifunction PCI to ISA Bridge Supports PCI at 30 MHz and 33 MHz Supports PCI Rev 2.1 Specification Supports Full ISA or Extended I/O (EIO) Bus Supports Full Positive Decode or Subtractive Decode of PCI Supports ISA and EIO at 1/4 of PCI Frequency Supports both Mobile and Desktop Deep Green Environments 3.3V Operation with 5V Tolerant Buffers Ultra-low Power for Mobile Environments Support Power-On Suspend, Suspend to RAM, Suspend to Disk, and SoftOFF System States All Registers Readable and Restorable for Proper Resume from 0.V Suspend Power Management Logic Global and Local Device Management Suspend and Resume Logic Supports Thermal Alarm Support for External Microcontroller Full Support for Advanced Configuration and Power Interface (ACPI) Revision 1.0 Specification and OS Directed Power Management Integrated IDE Controller Independent Timing of up to 4 Drives PIO Mode 4 and Bus Master IDE Transfers up to 14 Mbytes/sec Supports "Ultra DMA/33" Synchronous DMA Mode Transfers up to 33 Mbytes/sec
© INTEL CORPORATION 1997 April 1997
®
Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers Supports Glue-less "Swap-Bay" Option with Full Electrical Isolation
Enhanced DMA Controller Two 82C37 DMA Controllers Supports PCI DMA with 3 PC/PCI Channels and Distributed DMA Protocols (Simultaneously) Fast Type-F DMA for Reduced PCI Bus Usage Interrupt Controller Based on Two 82C59 15 Interrupt Support Independently Programmable for Edge/Level Sensitivity Supports Optional I/O APIC Serial Interrupt Input Timers Based on 82C54 System Timer, Refresh Request, Speaker Tone Output USB Two USB 1.0 Ports for Serial Transfers at 12 or 1.5 Mbit/sec Supports Legacy Keyboard and Mouse Software with USB-based Keyboard and Mouse Supports UHCI Design Guide SMBus Host Interface Allows CPU to Communicate Via SMBus Slave Interface Allows External SMBus Master to Control Resume Events Real-Time Clock 256-byte Battery-Back CMOS SRAM Includes Date Alarm Two 8-byte Lockout Ranges Microsoft Win95* Compliant 324 mBGA Package
Order Number: 290562-001
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82371AB (PIIX4)
The 82371AB PCI ISA IDE Xcelerator (PIIX4) is a multi-function PCI device implementing a PCI-to-ISA bridge function, a PCI IDE function, a Universal Serial Bus host/hub function, and an Enhanced Power Management function. As a PCI-to-ISA bridge, PIIX4 integrates many common I/O functions found in ISA-based PC systems--two 82C37 DMA Controllers, two 82C59 Interrupt Controllers, an 82C54 Timer/Counter, and a Real Time Clock. In addition to compatible transfers, each DMA channel supports Type F transfers. PIIX4 also contains full support for both PC/PCI and Distributed DMA protocols implementing PCI-based DMA. The Interrupt Controller has Edge or Level sensitive programmable inputs and fully supports the use of an external I/O Advanced Programmable Interrupt Controller (APIC) and Serial Interrupts. Chip select decoding is provided for BIOS, Real Time Clock, Keyboard Controller, second external microcontroller, as well as two Programmable Chip Selects. PIIX4 provides full Plug and Play compatibility. PIIX4 can be configured as a Subtractive Decode bridge or as a Positive Decode bridge. This allows the use of a subtractive decode PCI-to-PCI bridge such as the Intel 380FB PCIset which implements a PCI/ISA docking station environment. PIIX4 supports two IDE connectors for up to four IDE devices providing an interface for IDE hard disks and CD ROMs. Up to four IDE devices can be supported in Bus Master mode. PIIX4 contains support for "Ultra DMA/33" synchronous DMA compatible devices. PIIX4 contains a Universal Serial Bus (USB) Host Controller that is Universal Host Controller Interface (UHCI) compatible. The Host Controller's root hub has two programmable USB ports. PIIX4 supports Enhanced Power Management, including full Clock Control, Device Management for up to 14 devices, and Suspend and Resume logic with Power On Suspend, Suspend to RAM or Suspend to Disk. It fully supports Operating System Directed Power Management via the Advanced Configuration and Power Interface (ACPI) specification. PIIX4 integrates both a System Management Bus (SMBus) Host and Slave interface for serial communication with other devices.
Information in this document is provided in conjunction with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by the sale of Intel products. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The 82371AB PIIX4 may contain design defects or errors known as errata. Current characterized errata are available on request. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. Intel does not warrant or represent that such use will not infringe such rights. I2C is a two-wire communication bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementation of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Third-party brands and names are the property of their respective owners.
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82371AB
PCICLK AD[31:0] C/BE[3:0]# FRAME# TRDY# IRDY# STOP# DEVSEL# SERR# PAR IDSEL PHOLD# PHLKA# CLKRUN# RCIN# PWROK CPURST RSTDRV INIT PCIRST# IRQ0//GPO14 IRQ8#/GPI6 IRQ12/M INTR NMI IRQ[15,14,11:9,7:3,1] SERIRQ/GPI7 PRIQ[A:C] PIRQD IRQ9OUT#/GPO29 SMI# STPCLK# EXTSMI# SLP# SUSCLK BATLOW#/GPI9 PCI Bus Interface ISA Bus Interface System Reset SD[15:0] IOCS16# MEMCS16# MEMR# MEMW# AEN IOCHRDY IOCHK#/GPI0 SYSCLK BALE IOR# IOW# SMEMR# SMEMW# ZEROWS# SA[19:0] LA[23:17]/GPO[7:1] SBHE# Primary IDE Interface Interrupt PDCS1# PDCS3# PDA[2:0] PDD[15:0] PDDACK# PDDREQ PDIOIR# PDIOW# PIORDY SDCS1# SDCS3# SDA[2:0] SDD[15:0] SDDACK# SDDREQ SDIOR# SDIOW# SIORDY PCS[1:0]# XDIR#/GPO22 XOE#/GPO23 RTCALE/GPO25 FERR# IGNNE# BIOSCS# RTCCS#/GPO24 KBCCS#/GPO26 A20M# A20GATE MCCS# APICCS#/GPO13 APICACK#/GPO12 APCIREQ#/GPI5 RTCX[2:1] SMBALERT# SMBCLK SMBDATA GPI[21:13,1] GPI[12:2,0] (Multiplexed) GPO[30,28:27,8,0] GPO[29,26:9,7:1] (Multiplexed)
(PIIX4)
Secondary IDE Interface
THRM#/GPI8 LID//GPI10 RI#/GPI12 RSMRST# PWRBTN# SUSA# SUSB#/GPO15 SUSC#/GPO16
System Power Mgmt.
X-Bus Support Logic
ZZ/GPO19 PCIREQ[D:A]# SPKR OSC DREQ[7:5,3:0] DACK[7:5,3:0]# TC REFRESH# REQ[A:C]#/GPI[2:4] GNT[A:C]#/GPO[9:11] CLK48 USBPO± USBP1± OC[1:0]# CONFIG[2:1] TEST# Timers/ Counters I/O APIC Support Logic RTC DMA SMBUS
Universal Serial Bus Test
General Purpose Inputs and Outputs
Pix4_blk
Simplified Block Diagram
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82371AB (PIIX4)
CONTENTS
PAGE 1.0. ARCHITECTURAL OVERVIEW...........12 2.0. SIGNAL DESCRIPTION .............. 15 2.1. PIIX4 Signals .... 16 2.1.1. PCI Bus Interface......16 2.1.2. ISA Bus Interface......18 2.1.3. X-Bus Interface ... 21 2.1.4. DMA Signals ....... 23 2.1.5. Interrupt Controller/APIC Signals.........24 2.1.6. CPU Interface Signals ....... 26 2.1.7. Clocking Signals .......... 28 2.1.8. IDE Signals ......... 28 2.1.9. Universal Serial Bus Signals ...... 33 2.1.10. Power Management Signals.....33 2.1.11. General Purpose Input and Output Signals......35 2.1.12. Other System and Test Signals.........39 2.1.13. Power and Ground Pins............39 2.2. Power Planes....40 2.3. Power Sequencing Requirements ..... 41 3.0. REGISTER ADDRESS SPACE............42 3.1. PCI/ISA Bridge Configuration ............ 42 3.1.1. PCI Configuration Registers (Function 0)...........43 3.1.2. IO Space Registers ........... 44 3.2. IDE Configuration.......47 3.2.1. PCI Configuration Registers (Function 1)...........47 3.2.2. IO Space Registers ........... 48 3.3. Universal Serial Bus (USB) Configuration........48 3.3.1. PCI Configuration Registers (Function 2)...........48 3.3.2. IO Space Registers ........... 49 3.4. Power Management Configuration .... 50 3.4.1. IO Space Registers ........... 51 4.0. PCI TO ISA/EIO BRIDGE REGISTER DESCRIPTIONS......53 4.1. PCI to ISA/EIO Bridge PCI Configuration Space Registers (PCI Function 0)...........53 4.1.1. VID--Vendor Identification Register (Function 0)........53 4.1.2. DID--Device Identification Register (Function 0)........53 4.1.3. PCICMD--PCI Command Register (Function 0) ........ 54 4.1.4. PCISTS--PCI Device Status Register (Function 0)..........55 4.1.5. RID--Revision Identification Register (Function 0) ........... 55
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82371AB
(PIIX4)
4.1.6. CLASSC--Class Code Register (Function 0) .... 56 4.1.7. HEDT--Header Type Register (Function 0).......56 4.1.8. IORT--ISA I/O Recovery Timer Register (Function 0) ..... 56 4.1.9. XBCS--X-Bus Chip Select Register (Function 0) ....... 57 4.1.10. PIRQRC[A:D]--PIRQX Route Control Registers (Function 0) ......... 59 4.1.11. SERIRQC--Serial IRQ Control Register (Function 0) .... 59 4.1.12. TOM--Top of Memory Register (Function 0) ... 60 4.1.13. MSTAT--Miscellaneous Status Register (Function 0)....61 4.1.14. MBDMA[1:0]--Motherboard Device DMA Control Registers (Function 0).......61 4.1.15. APICBASE--APIC Base Address Relocation Register (Function 0)......62 4.1.16. DLC--Deterministic Latency Control Register (Function 0).....62 4.1.17. PDMACFG--PCI DMA Configuration Register (Function 0)....63 4.1.18. DDMABP--Distributed DMA Slave Base Pointer Registers (Function 0)........64 4.1.19. GENCFG--General Configuration Register (Function 0) ........ 65 4.1.20. RTCCFG--Real Time Clock Configuration Register (Function 0) .... 67 4.2. PCI to ISA/EIO Bridge IO Space Registers (IO) ....... 68 4.2.1. DMA Registers....68 4.2.1.1. DCOM--DMA Command Register (IO).......68 4.2.1.2. DCM--DMA Channel Mode Register (IO)...69 4.2.1.3. DR--DMA Request Register (IO).......70 4.2.1.4. WSMB--Write Single Mask Bit (IO) ............ 70 4.2.1.5. RWAMB--Read/Write All Mask Bits (IO) .... 71 4.2.1.6. DS--DMA Status Register (IO) .......... 71 4.2.1.7. DBADDR--DMA Base and Current Address Registers (IO) ....... 72 4.2.1.8. DBCNT--DMA Base and Current Count Registers (IO).....72 4.2.1.9. DLPAGE--DMA Low Page Registers (IO)..73 4.2.1.10. DCBP--DMA Clear Byte Pointer Register (IO)........73 4.2.1.11. DMC--DMA Master Clear Register (IO) ... 73 4.2.1.12. DCLM--DMA Clear Mask Register (IO)....74 4.2.2. Interrupt Controller Registers......74 4.2.2.1. ICW1--Initialization Command Word 1 Register (IO) ......... 74 4.2.2.2. ICW2--Initialization Command Word 2 Register (IO) ......... 75 4.2.2.3. ICW3--Initialization Command Word 3 Register (IO) ......... 75 4.2.2.4. ICW3--Initialization Command Word 3 Register (IO) ......... 76 4.2.2.5. ICW4--Initialization Command Word 4 Register (IO) ......... 76 4.2.2.6. OCW1--Operational Control Word 1 Register (IO)....77 4.2.2.7. OCW2--Operational Control Word 2 Register (IO)....77 4.2.2.8. OCW3-- Operational Control Word 3 Register (IO)............78 4.2.2.9. ELCR1--Edge/Level Control Register (IO) .......... 79 4.2.2.10. ELCR2--Edge/Level Control Register (IO) ........ 79 4.2.3. Counter/Timer Registers....80 4.2.3.1. TCW--Timer Control Word Register (IO)....80 4.2.3.2. TMRSTS--Timer Status Registers (IO) ...... 82
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