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Details, datasheet, quote on part number:440MX-100
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Datasheet text preview:
82443MX100 PCIset
Datasheet
§ Processor Host Bus Support Optimized for the Intel® mobile Pentium® II and the mobile CeleronTM processors at 100 MHz or 66 MHz GTL+ Bus Driver Technology § Integrated DRAM Support -- 8 MB to 256 MB using 16-Mb, 64-Mb, and 128-Mb Technology -- Standard and Registered SDRAM (Synchronous) DRAM Support (x-1-1-1 access at 100 MHz or 66 MHz) Enhanced Open Page Arbitration SDRAM Paging Scheme § PCI Bus Interface PCI Rev. 2.3, 3.3-V, 33-MHz Interface Compliant § Integrated IDE Controller One Channel Support for "Ultra DMA/33" Synchronous DMA Mode § System Peripheral Support Enhanced DMA Controller Support for Dual Cascaded 82C37 Controllers Interrupt Controller based on two 82C59 for up to 15 Interrupts System Timer based on 82C54 Real Time Clock with 256-Bytes Battery backed RAM X-bus Support for SIO, KBCX, and Flash USB AC' 7 Link Controller 9 AC' 7 Audio Modem CODEC 9 Interface Support USB 1.1 Port for Serial Transfers at 12 or 1.5 Mbits/sec Supports UHCI Design Guide SMBus Support Power Management Logic Support for Power-On-Suspend, Suspend-To-SDRAM, and Suspend-To-Disk Support for Thermal Alarm Full Support for ACPI Specification Revision 1.0 31 GPIO Pins Thermal Design Power 2.1W for 100 MHz 1.6W for 66 MHz 492 uBGA Package
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The Intel 82443MX100 PCIset integrates the traditional "North Bridge" and "South Bridge" into one device, which reduces power and board space for Intel mobile Pentium II processor-based designs and mobile Celeron processor-based designs. The Intel 82443MX100 PCIset may contain design defects or errors know as errata, which may cause the product to deviate from published specifications. Current characterized errata are available upon request.
Order Number- 245292-001
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The mobile CeleronTM processor, mobile Pentium® II processor, and 82443MX100 controller products may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. The Intel 82443MX100 PCIset Datasheet is provided "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect IL 60056-7641 or call 1-800-879-4683 *Other brands and names are the property of their respective owners. Copyright © Intel Corporation, 1999.
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Datasheet
Intel® 82443MX100 PCIset
CONTENTS
1.0 Introduction ......... 1 1.1 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 440MX Feature Summary .......... 2 1.3 440MX Features....... 3 Architecture Overview........ 6 Signal Description and Pin States ....... 7 Pin List...... 7 3.1.1 Signal Description.......... 8 3.1.2 Power and Ground Pins..... 19 3.2 GPIO Definition ...... 20 3.3 Power Rail Overview ....... 22 3.4 Power-up State Initial Value ........... 23 3.5 Power-On-Reset Pin Values........... 24 3.6 Power-up/Reset Strap Options ....... 30 3.7 CPU Reset............. 31 Power Planes ..... 33 4.1 Overview .......... 33 4.2 RTC Power Plane ........... 33 4.3 Resume Power Plane...... 33 System Address Map........ 35 5.1 5.2 Addressable Memory Support ........ 35 Memory Map.......... 35 5.2.1 Compatibility Area ....... 37 5.2.1.1 DOS Area (00000h-9FFFh; 0 - 640 KB) ...... 38 5.2.1.2 Video Buffer Area (A0000h-BFFFFh; 640 - 768 KB)... 38 5.2.1.3 Expansion Area (C0000h-DFFFFh; 768 - 896 KB) ..... 38 5.2.1.4 Extended System BIOS Area (E0000h-EFFFFh; 896 - 960 KB) .... 38 5.2.1.5 System BIOS Area (F0000h-FFFFFh; 960 KB - 1 MB) ........ 38 5.2.2 Extended Memory Area ..... 39 5.2.2.1 Main DRAM Address Range (0010_0000h to Top of Main Memory) ........... 39 5.2.2.2 Extended SMRAM Address Range (Top of Main Memory TSEG_SZ to Top of Main Memory).... 39 5.2.2.3 PCI Memory Address Range (Top of Main Memory to 4 GB) .. ......... 39 5.2.2.4 High BIOS Area (FFC0_0000h - FFFF_FFFFh) ......... 39 System Management Mode (SMM) Memory Range......... 40 Memory Shadowing......... 40 Decode Rules and Cross-Bridge Address Mapping ......... 40 5.5.1 PCI Interface Memory Decode Rules ......... 40 5.5.2 Legacy VGA Range ........... 40 I/O Address Space .......... 41 3.1
2.0 3.0
4.0
5.0
5.3 5.4 5.5
5.6
Datasheet
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Intel® 82443MX100 PCIset
6.0
5.6.1 Fixed I/O Address Ranges .......... 41 5.6.2 Variable I/O Decode Ranges....... 45 Functional Description ..... 48 6.1 Mobile Celeron Processor and Mobile Pentium II Processor Host Interface ...... 48 6.1.1 Overview ............ 48 6.1.2 Host Bus Device Support............ 48 6.1.3 Special Cycles .... 49 6.1.4 Symmetric Multiprocessor (SMP) Configuration .. 50 6.1.5 In-order Queue Pipelining ........... 50 6.1.6 Frame Buffer Memory Support (USWC)..... 50 6.1.7 CPU Sideband Interface .... 51 6.1.7.1 A20M#........ 51 6.1.7.2 FERR#/IGNNE# (Co-processor Error) ........ 51 6.1.7.3 INIT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.7.4 Interrupt Signals ........ 52 6.1.7.5 NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 6.1.7.6 SMI# .......... 52 6.1.7.7 STPCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Memory Interface ............ 53 6.2.1 DRAM Interface .. 53 6.2.1.1 DRAM Interface Overview ........ 53 6.2.2 DRAM Organization and Configuration ...... 53 6.2.2.1 Configuration Mechanism for DIMMs .......... 55 6.2.2.1.1 Memory Detection and Initialization......... 55 6.2.2.1.2 SMBus Configuration ...... 56 6.2.2.1.3 Accessing the Serial Presence Detect Ports..... 56 6.2.2.1.4 DRAM Register Programming.. 56 6.2.3 SDRAM Cycle Encoding .... 57 6.2.4 DRAM Address Translation and Decoding .......... 62 6.2.5 SDRAMC Register Programming ......... 63 6.2.6 SDRAM Paging Policy ....... 64 6.2.6.1 Overview .......... 64 6.2.6.2 Open Page Arbitration Policies .......... 64 6.2.6.3 Selective Auto Precharge Policy ........ 64 6.2.7 DRAM Power Throttling ..... 64 6.2.7.1 Overview .......... 64 6.2.7.2 Conceptual Description of Power Throttling....... 64 6.2.7.2.1 During Monitoring Regime ....... 64 6.2.7.2.2 During Throttling Regime ......... 65 6.2.7.2.3 Read and Write Throttling Regimes......... 65 6.2.7.2.4 The Relation Between Read and Write Throttling . ...... 66 6.2.7.3 SDRAM Power Throttling Setting Sequence ..... 66 6.2.8 SDRAM Performance Description ........ 66 6.2.9 SDRAM Optimizations ....... 66 6.2.9.1 Dual and Quad Bank Support ............ 66 System Memory Management........ 67 6.3.1 SMRAM Range Overview ........... 67 Datasheet
6.2
6.3
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Intel® 82443MX100 PCIset
6.4
6.5
6.6
6.3.2 Compatible SMRAM (C_SMRAM)........ 67 6.3.3 Extended SMRAM (E_SMRAM).. 68 AC' 7 Audio and Modem Controller......... 71 9 6.4.1 AC' 7 Audio Controller ...... 71 9 6.4.2 AC' 7 Modem Controller............ 71 9 6.4.3 AC' 7 Overview.. 72 9 6.4.4 System Initialization ........... 73 6.4.5 Clocking .... 73 6.4.6 Digital Interface... 73 6.4.6.1 Multi-Point ACLink..... 73 6.4.6.1.1 Primary Codec....... 74 6.4.6.1.2 Secondary Codec ........... 74 6.4.6.2 AC-link Digital Serial Interface Protocol....... 74 PCI Interface.......... 76 6.5.1 PCI Interface Overview ...... 76 6.5.2 North Bridge/Cluster Functionality........ 77 6.5.2.1 North Bridge/Cluster as a PCI Target.......... 77 6.5.2.2 North Bridge/Cluster as a PCI Initiator ........ 78 6.5.2.3 Delayed Transactions ......... 79 6.5.3 South Bridge/Cluster Functionality ....... 80 6.5.3.1 South Bridge/Cluster as a PCI Target ......... 80 6.5.3.2 South Bridge/Cluster as a PCI Initiator........ 81 DMA Controller ...... 82 6.6.1 Register Description .......... 82 6.6.2 Functional Description ....... 82 6.6.2.1 DMA Transfer Modes.......... 83 6.6.2.1.1 Single Transfer Mode...... 84 6.6.2.1.2 Block Transfer Mode....... 84 6.6.2.1.3 Demand Transfer Mode .. 84 6.6.2.1.4 Cascade Mode....... 84 6.6.2.2 DMA Transfer Types.. 84 6.6.2.2.1 Read Transfers...... 84 6.6.2.2.2 Write Transfers ...... 85 6.6.2.2.3 Verify Transfer ....... 85 6.6.2.3 DMA Timings.... 85 6.6.2.3.1 DMA Buffer for Bompatible Transfers...... 85 6.6.2.3.2 DREQ And DACK# Latency Control........ 85 6.6.2.4 X-bus/DMA Arbitration ........ 85 6.6.2.4.1 Channel Priority ..... 86
6.6.2.4.1.1 Fixed Priority ......86 6.6.2.4.1.2 Rotating Priority..87
6.6.2.5
6.6.2.6
6.6.2.4.2 Arbitration During Non-Maskable Interrupts...... 88 Register Functionality ......... 88 6.6.2.5.1 Address Compatibility Mode..... 88 6.6.2.5.2 Summary of DMA Transfer Sizes ............ 88 6.6.2.5.3 Address Shifting When Programmed for 16-Bit ... I/O Count by Words ........ 89 6.6.2.5.4 Autoinitialize .... 89 Software Commands .......... 89 6.6.2.6.1 Clear Byte Pointer Flip-Flop ..... 89 Datasheet iii
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