Details, datasheet, quote on part number: 440MX
Part440MX
CategoryInterface and Interconnect => Chipsets
DescriptionIntel 440MX Chipset Electrical And Thermal Specificationaddendum
CompanyIntel Corporation
DatasheetDownload 440MX datasheet
  

 

Features, Applications

Processor Host Bus Support Optimized for the Intel® Pentium® II and mobile CeleronTM processors at 66 MHz GTL+ Bus Driver Technology System Timer based on 82C54 Real Time Clock w/ 256 Bytes Battery-backed RAM X-bus Support for SIO, KBCX and Flash

Integrated DRAM Support 256 MB using 16-/64/128-Mb Technology Standard and Registered SDRAM (Synchronous) DRAM Support (x-1-1-1 access at 66 MHz) Enhanced Open Page Arbitration SDRAM Paging Scheme

AC'97 Audio and Modem CODEC Interface Support USB 1.1 Port for Serial Transfers or 1.5 Mbits/sec Supports UHCI Design Guide

SMBus Support Power Management Logic Support for Power-on Suspend, Suspend-to-SDRAM, and Suspend-to-Disk Support for Thermal Alarm Full Support for ACPI Revision 1.0 Specification

Integrated IDE Controller 1 Channel Support for "Ultra DMA/33" Synchronous DMA Mode

System Peripheral Support Enhanced DMA Controller Support for Dual Cascaded 82C37 Controllers Interrupt Controller based on two 82C59 for to 15 Interrupts

The Intel® 82443MX PCIset integrates the traditional "North Bridge" and "South Bridge" into one device reducing power and board space for Intel® Pentium® II and mobile CeleronTM processor-based designs. The Intel 82443MX PCIset may contain design defects or errors know as errata which may cause the product to deviate from published specifications. Current characterized errata are available upon request.

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by the sale of Intel products. Except as provided in Intel's terms and conditions of sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local sales office or your distributor to obtain the latest specifications before placing your product order. Mobile CeleronTM (Micro-PGA and BGA) processors may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available upon request. Copies of documents that have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling or by visiting Intel's web site at http://www.intel.com. Copyright © Intel Corporation is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the 2 C bus/protocol and was developed by Intel. Implementations of the 2 C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. * Third party brands and names are the property of their respective owners.

PAGE 1. INTRODUCTION...................................................................................................................................... 82440MX Chipset Feature Summary.............................................................................................. 1 82440MX Chipset Features............................................................................................................ 2

ARCHITECTURE OVERVIEW................................................................................................................. 5 REFERENCES......................................................................................................................................... 6 SIGNAL DESCRIPTION AND PIN STATES............................................................................................. 7 4.1 Pin List........................................................................................................................................... Signal Description............................................................................................................. 8 Power and Ground Pins.................................................................................................. 22

GPIO Definition............................................................................................................................. 23 Power Rail Overview.................................................................................................................... 26 Power-Up State Initial Value......................................................................................................... 27 Power-On Reset Pin Values......................................................................................................... 27 Power-Up/Reset Strap Options..................................................................................................... 35 CPU Reset................................................................................................................................... 37

POWER PLANES................................................................................................................................... Overview...................................................................................................................................... 38 RTC Power Plane......................................................................................................................... 38 Resume Power Plane................................................................................................................... 38

SYSTEM ADDRESS MAP...................................................................................................................... 6.1 6.2 Addressable Memory Support...................................................................................................... 40 Memory Map................................................................................................................................. 40 6.2.1 Compatibility Area........................................................................................................... DOS Area - 640 KB).................................................... 43 Video Buffer Area - 768 KB).................................. 43 Expansion Area - 896 KB).................................... 43 Extended System BIOS Area - 960 KB)................ 43 System BIOS Area - 1 MB).............................. 43 Main DRAM Address Range (0010_0000h to Top of Main Memory)......... 44 Extended SMRAM Address Range (Top of Main Memory - TSEG_SZ to Top of Main Memory)................................................................................ 44 iii


 

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