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Details, datasheet, quote on part number:80960J
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Datasheet text preview:
PRELIMINARY
80960JA/JF EMBEDDED 32-BIT MICROPROCESSOR
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Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture -- One Instruction/Clock Execution -- Load/Store Programming Model -- Sixteen 32-Bit Global Registers -- Sixteen 32-Bit Local Registers (8 sets) -- Nine Addressing Modes -- User/Supervisor Protection Model Two-Way Set Associative Instruction Cache -- 80960JA - 2 Kbyte -- 80960JF - 4 Kbyte -- Programmable Cache Locking Mechanism Direct Mapped Data Cache -- 80960JA - 1 Kbyte -- 80960JF - 2 Kbyte -- Write Through Operation On-Chip Stack Frame Cache -- Seven Register Sets Can Be Saved -- Automatic Allocation on Call/Return -- 0-7 Frames Reserved for High-Priority Interrupts On-Chip Data RAM -- 1 Kbyte Critical Variable Storage -- Single-Cycle Access
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-- 32-Bit Multiplexed Address/Data -- Programmable Memory Configuration -- Selectable 8-, 16-, 32-Bit Bus Widths -- Supports Unaligned Accesses -- Big or Little Endian Byte Ordering New Instructions -- Conditional Add, Subtract and Select -- Processor Management High-Speed Interrupt Controller -- 31 Programmable Priorities -- Eight Maskable Pins plus NMI -- Up to 240 Vectors in Expanded Mode Two On-Chip Timers -- Independent 32-Bit Counting -- Clock Prescaling by 1, 2, 4 or 8 -- lnternal Interrupt Sources Halt Mode for Low Power Compatibility
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s IEEE 1149.1 (JTAG) Boundary Scan s Packages
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-- 132-Lead Pin Grid Array (PGA) -- 132-Lead Plastic Quad Flat Pack (PQFP)
132 PIN 1 99
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Figure 1. 80960JA/JF Microprocessors
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information contained herein supersedes previously published specifications on these devices from Intel. © INTEL CORPORATION, 1995 September 1995 Order Number: 272504-004
80960JA/JF
80960JA/JF EMBEDDED 32-BIT MICROPROCESSOR
1.0 PURPOSE ........1 2.0 80960JA/JF OVERVIEW ..........1 2.1 80960 Processor Core ......2 2.2 Burst Bus ...........2 2.3 Timer Unit ..........3 2.4 Priority Interrupt Controller ........3 2.5 Instruction Set Summary ...........3 2.6 Faults and Debugging .......3 2.7 Low Power Operation .......4 2.8 Test Features .....4 2.9 Memory-Mapped Control Registers ..........4 2.10 Data Types and Memory Addressing Modes ...4 3.0 PACKAGE INFORMATION ......6 3.1 Pin Descriptions .......... 6 3.1.1 Functional Pin Definitions ........6 3.1.2 80960Jx 132-Lead PGA Pinout ............13 3.1.3 80960Jx PQFP Pinout ..17 3.2 Package Thermal Specifications ............20 4.0 ELECTRICAL SPECIFICATIONS ...22 4.1 Absolute Maximum Ratings .....22 4.2 Operating Conditions ......22 4.3 Connection Recommendations .........22 4.4 DC Specifications ...........23 4.5 AC Specifications ............25 4.5.1 AC Test Conditions and Derating Curves .......32 4.5.2 AC Timing Waveforms ...33 5.0 BUS FUNCTIONAL WAVEFORMS .........41 6.0 DEVICE IDENTIFICATION .....55 7.0 REVISION HISTORY .............55
PRELIMINARY
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80960JA/JF
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IGURES Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. 80960JA/JF Microprocessors ..........0 80960JA/JF Block Diagram ........2 132-Lead Pin Grid Array Bottom View - Pins Facing Up .......... 13 132-Lead Pin Grid Array Top View - Pins Facing Down .. 14 132-Lead PQFP - Top View ........... 17 AC Test Load .......... 32 Output Delay or Hold vs. Load Capacitance .......... 32 Rise and Fall Time Derating ........... 33 CLKIN Waveform ............ 33 Output Delay Waveform for TOV1 ............ 34 Output Float Waveform for TOF ...... 34 Input Setup and Hold Waveform for TIS1 and TIH1 .......... 35 Input Setup and Hold Waveform for TIS2 and TIH2 .......... 35 Input Setup and Hold Waveform for TIS3 and TIH3 .......... 36 Input Setup and Hold Waveform for TIS4 and TIH4 .......... 36 Relative Timings Waveform for TLXL and T LXA ...... 37 DT/R and DEN Timings Waveform ......... 37 TCK Waveform ....... 38 Input Setup and Hold Waveforms for T BSIS1 and T BSIH1 .......... 38 Output Delay and Output Float Waveform for TBSOV1 and TB S O F 1 ......... 39 Output Delay and Output Float Waveform for TBSOV2 and TB S O F 2 ......... 39 Input Setup and Hold Waveform for TBSIS2 and TB S I H 2 .. 40 Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus ....... 41 Burst Read and Write Transactions Without Wait States, 32-Bit Bus ..... 42 Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus ...... 43 Burst Read and Write Transactions Without Wait States, 8-Bit Bus ....... 44 Burst Read and Write Transactions With 1, 0 Wait States and Extra Tr State on Read, 16-Bit Bus .. 45 Bus Transactions Generated by Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian 46
HOLD/HOLDA Waveform For Bus Arbitration ........ 47 Cold Reset Waveform ..... 48 Warm Reset Waveform ... 49 Entering the ONCE State ......... 50 Summary of Aligned and Unaligned Accesses (32-Bit Bus) .... 53 Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ........ 54
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80960JA/JF
TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. 80960Jx Instruction Set ....5 Pin Description Nomenclature .........6 Pin Description -- External Bus Signals ..7 Pin Description -- Processor Control Signals, Test Signals and Power .......... 10 Pin Description -- Interrupt Unit Signals ......... 12 132-Lead PGA Pinout -- In Signal Order ........ 15 132-Lead PGA Pinout -- In Pin Order ... 16 132-Lead PQFP Pinout -- In Signal Order ........... 18 132-Lead PQFP Pinout -- In Pin Order .......... 19 132-Lead PGA Package Thermal Characteristics .......... 20 132-Lead PQFP Package Thermal Characteristics ....... 21 80960JA/JF Operating Conditions ......... 22 80960JA/JF DC Characteristics .... 23 80960JA/JF IC C Characteristics .... 23 80960JA/JF AC Characteristics (33 MHz) ....... 25 Note Definitions for Table 15, 80960JA/JF AC Characteristics (33 MHz) ....... 27 80960JA/JF AC Characteristics (25 MHz) ....... 27 80960JA/JF AC Characteristics (16 MHz) ....... 29 Natural Boundaries for Load and Store Accesses ......... 51 Summary of Byte Load and Store Accesses ......... 51 Summary of Short Word Load and Store Accesses ....... 51 Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4) ..... 52 80960JA/JF Die and Stepping Reference ....... 55 Data Sheet Version -003 to -004 Revision History ......... 55 Data Sheet Version -002 to -003 Revision History ......... 56 Data Sheet Version -001 to -002 Revision History ......... 57 Data Sheet Version -002 to -003 Revision History ......... 58
PRELIMINARY
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80960JA/JF
1.0 PURPOSE
This document contains preliminary information for the 80960JA/JF microprocessor, including electrical characteristics and package pinout information. Detailed functional descriptions -- other than parametric performance -- are published in the i960® Jx Microprocessor User's Guide (272483). Throughout this data sheet, references to "80960Jx" indicate features which apply to all of the following: · 80960JA -- 5V, 2 Kbyte instruction cache, 1 Kbyte data cache · 80960JF -- 5V, 4 Kbyte instruction cache, 2 Kbyte data cache · 80960JD -- 5V, 4 Kbyte instruction cache, 2 Kbyte data cache and clock doubling · 80L960JA -- 3.3 V version of the 80960JA · 80L960JF -- 3.3 V version of the 80960JF configuration registers enable the processor to operate with all combinations of bus width and data object alignment. The processor supports a homogeneous byte ordering model. This processor integrates two important peripherals: a timer unit and an interrupt controller. These and other hardware resources are programmed through memory-mapped control registers, an extension to the familiar 80960 architecture. The timer unit (TU) offers two independent 32-bit timers for use as real-time system clocks and general-purpose system timing. These operate in either single-shot or auto-reload mode and can generate interrupts. The interrupt controller unit (ICU) provides a flexible, low-latency means for requesting interrupts.The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. The ICU takes advantage of a cached priority table and optional routine caching to minimize interrupt latency. Local registers may be dedicated to high-priority interrupts to further reduce latency. Acting independently from the core, the ICU compares the priorities of posted interrupts with the current process priority, offloading this task from the core. The ICU also supports the integrated timer interrupts. The 80960JA/JF features a Halt mode designed to support applications where low power consumption is critical. The halt instruction shuts down instruction execution, resulting in a power savings of up to 90 percent. The 80960JA/JF's testability features, including ONCE (On-Circuit Emulation) mode and Boundary Scan (JTAG), provide a powerful environment for design debug and fault diagnosis. The Solutions960® program features a wide variety of development tools which support the i960 processor family. Many of these tools are developed by partner companies; some are developed by Intel, such as profile-driven optimizing compilers. For more information on these products, contact your local Intel representative.
2.0
80960JA/JF OVERVIEW
The 80960JA/JF offers high performance to costsensitive 32-bit embedded applications. The 80960JA/JF is object code compatible with the 80960 Core Architecture and is capable of sustained execution at the rate of one instruction per clock. This processor's features include generous instruction cache, data cache and data RAM. It also boasts a fast interrupt mechanism, dual programmable timer units and new instructions. Memory subsystems for cost-sensitive embedded applications often impose substantial wait state penalties. The 80960JA/JF integrates considerable storage resources on-chip to decouple CPU execution from the external bus. The 80960JA/JF rapidly allocates and deallocates local register sets during context switches. The processor needs to flush a register set to the stack only when it saves more than seven sets to its local register cache. A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A full complement of control signals simplifies the connection of the 80960JA/JF to external components. The user programs physical and logical memory attributes through memory-mapped control registers (MMRs) -- an extension not found on the i960 Kx, Sx or Cx processors. Physical and logical
PRELIMINARY
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