Details, datasheet, quote on part number: 80C196KC
CategoryMicrocontrollers => CISC->X86/X96 Family
TitleCISC->X86/X96 Family
DescriptionCommercial/express Chmos Microcontroller
CompanyIntel Corporation
DatasheetDownload 80C196KC datasheet
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Features, Applications

80C196KC 16 and 20 MHz Available 488 Byte Register RAM 28 Interrupt Sources 16 Vectors Peripheral Transaction Server x 16 Multiply (20 MHz) 32 16 Divide (20 MHz) Powerdown and Idle Modes Five I O Ports 16-Bit Watchdog Timer Extended Temperature Available 16 Kbytes of On-Chip OTPROM 16 Kbytes ROM ROMless Y Dynamically Configurable or 16-Bit Buswidth

Full Duplex Serial Port High Speed I O Subsystem 16-Bit Timer 16-Bit Up Down Counter with Capture 3 Pulse-Width-Modulated Outputs Four 16-Bit Software Timers A D Converter with Sample Hold HOLD HLDA Bus Protocol OTPROM One-Time Programmable Version

The 80C196KC 16-bit microcontroller is a high performance member of the MCS 96 microcontroller family The is an enhanced 80C196KB device with 488 bytes RAM 16 and 20 MHz operation and an optional 16 Kbytes of ROM OTPROM Intel's CHMOS III process provides a high performance processor along with low power consumption The an 80C196KC with 16 Kbytes on-chip OTPROM The an 80C196KC with 16 Kbytes factory programmed ROM In this document the 80C196KC will refer to all products unless otherwise stated Four high-speed capture inputs are provided to record times when events occur Six high-speed outputs are available for pulse or waveform generation The high-speed output can also generate four software timers or start A D conversion Events can be based on the timer or up down counter With the commercial (standard) temperature option operational characteristics are guaranteed over the temperature range 70 C With the extended (Express) temperature range option operational characteristics are guaranteed over the temperature range 85 C Unless otherwise noted the specifications are the same for both options See the Packaging information for extended temperature designators

Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata

This device is manufactured 9 a CHMOS III process Additional process and reliability information is available in Intel's Components Quality and Reliability Handbook Order Number 210997

Table 2 8XC196KC Memory Map Description External Memory I O Internal ROM OTPROM or External Memory (Determined by EA) Reserved Must contain FFH (Note 5) PTS Vectors Upper Interrupt Vectors ROM OTPROM Security Key Reserved Must contain FFH (Note 5)

Reserved Must Contain 20H (Note 5) CCB Reserved Must contain FFH (Note 5) Lower Interrupt Vectors

EXAMPLE is 68-Lead PLCC OTPROM 16 MHz For complete package dimensional data refer to the Intel Packaging Handbook (Order Number 240800)

NOTE 1 EPROMs are available as One Time Programmable (OTPROM) only
Port 3 and Port 4 External Memory 488 Bytes Register RAM (Note 1)

Figure 3 The 8XC196KC Family Nomenclature Table 1 Thermal Characteristics Package Type PLCC QFP SQFP ija C W TBD ijc C W TBD

All thermal impedance data is approximate for static air conditions 1W of power dissipation Values will change depending on operation conditions and application See the Intel Packaging Handbook (order number 240800) for a description of Intel's thermal impedance test methodology

NOTES 1 Code executed in locations to 01FFH will be forced external 2 Reserved memory locations must contain 0FFH unless noted 3 Reserved SFR bit locations must contain 0 4 Refer to 8XC196KC User's manual for SFR descriptions 5 WARNING Reserved memory locations must not be written or read The contents and or function of these locations may change with future revisions of the device Therefore a program that relies on one or more of these locations may not function properly


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