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87C51 80C51BH 80C31BH CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Commercial Express
87C51 80C51BH 80C51BHP 80C31BH See Table 1 for Proliferation Options
Y Y Y
High Performance CHMOS EPROM 24 MHz Operation Improved Quick-Pulse Programming Algorithm 3-Level Program Memory Lock Boolean Processor 128-Byte Data RAM 32 Programmable I O Lines Two 16-Bit Timer Counters Extended Temperature Range ( b 40 C to a 85 C)
Y Y Y
5 Interrupt Sources Programmable Serial Port TTL- and CMOS-Compatible Logic Levels 64K External Program Memory Space 64K External Data Memory Space ONCE Mode Facilitates System Testing Power Control Modes Idle Power Down
Y Y Y Y Y Y
Y Y Y Y
MEMORY ORGANIZATION
PROGRAM MEMORY Up to 4 Kbytes of the program memory can reside on-chip (except 80C31BH) In D addition the device can address up to 64K of program memory external to the chip ATA MEMORY This microcontroller has a 128 x 8 on-chip RAM In addition it can address up to 64 Kbytes of T external data memory he Intel 87C51 80C51BH 80C31BH is a single-chip control-oriented microcontroller which is fabricated on Intel's reliable CHMOS III-E technology Being a member of the MCS 51 controller family the 87C51 80C51BH 80C31BH uses the same powerful instruction set has the same architecture and is pin-forT pin compatible with the existing MCS 51 controller family of products he 80C51BHP is identical to the 80C51BH When ordering the 80C51BHP customers must submit the 64 byte encryption table together with the ROM code Lock bit 1 will be set to enable the internal ROM code T protection and at the same time allows code verification he extremely low operating power along with the two reduced power modes Idle and Power Down make this part very suitable for low power applications The Idle mode freezes the CPU while allowing the RAM imer counters serial port and interrupt system to continue functioning The Power Down mode saves the F RAM contents but freezes the oscillator causing all other chip functions to be inoperative or the remainder of this document the 87C51 80C51BH and 80C31BH will be referred to as the 87C51 BH unless information applies to a specific device
I Other brands and names are the property of their respective owners nformation in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata O COPYRIGHT INTEL CORPORATION 1995 ctober 1995 Order Number 272335-003
87C51 80C51BH 80C31BH
Table 1 Proliferation Options Standard 80C31BH 80C51BH 80C51BHP 87C51
NOTES 3 5 -1 3 5 -2 0 5 -24 3 5 MHz MHz MHz MHz to to to to 12 16 12 24 MHz MHz MHz MHz VCC VCC VCC VCC
e e e e
-1 X X X X
-2 X X X X
-24 X X X X
X X X X
5V 5V 5V 5V
g 20% g 20% g 20% g 20%
272335 1
Figure 1 87C51 BH Block Diagram
2
87C51 80C51BH 80C31BH
PROCESS INFORMATION
The 87C51 BH is manufactured on the CHMOS III-E process Additional process and reliability information is available in Intel's Components Quality and Reliability Handbook Order No 210997
PACKAGES
Part 87C51 BH Prefix P D N S Package Type 40-Pin Plastic DIP (OTP) 40-Pin CERDIP (EPROM) 44-Pin PLCC (OTP) 44-Pin QFP (OTP)
272335 3 272335 2
PLCC
DIP
272335 4
Do not connect reserved pins
QFP
Figure 2 Pin Connections
3
87C51 80C51BH 80C31BH
ort 2 also receives some control signals and the high-order address bits during EPROM programming P and program verification ort 3 Port 3 is an 8-bit bidirectional I O port with internal pullups The Port 3 output buffers can drive LS TTL inputs Port 3 pins that have 1's written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are externally pulled low will source current PIL on the data sheet) because of the pullups (I ort 3 also serves the functions of various special feP tures of the MCS-51 Family as listed below a in P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 Name RXD TXD INT0 INT1 T0 T1 WR RD Alternate Function Serial input line Serial output line External Interrupt 0 External Interrupt 1 Timer 0 external input Timer 1 external input External Data Memory Write strobe External Data Memory Read strobe
PIN DESCRIPTION
VCC Supply voltage during normal Idle and Power V Down operations P SS Circuit ground ort 0 Port 0 is an 8-bit open drain bidirectional I O port As an output port each pin can sink several LS TTL inputs Port 0 pins that have 1's written to them float and in that state can be used as high-impedP ance inputs ort 0 is also the multiplexed low-order address and data bus during accesses to external memory In this application it uses strong internal pullups when emitP ting 1's ort 0 also receives the code bytes during EPROM programming and outputs the code bytes during program verification External pullups are required P during program verification ort 1 Port 1 is an 8-bit bidirectional I O port with internal pullups The Port 1 output buffers can drive LS TTL inputs Port 1 pins that have 1's written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 1 pins that are externally pulled low will source current (IIL on the data sheet) because of the internal pullP ups ort 1 also receives the low-order address bytes during EPROM programming and program verificaP tion ort 2 Port 2 is an 8-bit bidirectional I O port with internal pullups Port 2 pins that have 1's written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 2 pins that are externally pulled low will source current (IIL on the data sheet) because of the internal pullP ups ort 2 emits the high-order address byte during fetches from external Program memory and during accesses to external Data Memory that use 16-bit address (MOVX DPTR) In this application it uses D strong internal pullups when emitting 1's uring accesses to external Data Memory that use 8-bit addresses (MOVX Ri) Port 2 emits the contents of the P2 Special Function Register 4
Port 3 also receives some control signals for R EPROM programming and program verification ST Reset input A high on this pin for two machine cycles while the oscillator is running resets the device The port pins will be driven to their reset condition when a minimum VIH1 voltage is applied whether the oscillator is running or not An internal pulldown resistor permits a power-on reset with only a capacitor connected to VCC A LE PROG Address Latch Enable output signal for latching the low byte of the address during accesses to external memory This pin is also the program pulse input (PROG) during EPROM programming for I the 87C51 f desired ALE operation can be disabled by setting bit 0 of SFR location 8EH With this bit set the pin is weakly pulled high However the ALE disable feature will be suspended during a MOVX or MOVC instruction idle mode power down mode and ICE mode The ALE disable feature will be terminated by reset When the ALE disable feature is suspended or terminated the ALE pin will no longer be pulled up P weakly Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode
87C51 80C51BH 80C31BH
In normal operation ALE is emitted at a constant rate of 1 6 the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped during each P access to external Data Memory SEN Program Store Enable is the Read strobe to External Program Memory When the 87C51 BH is executing from Internal Program Memory PSEN is inactive (high) When the device is executing code from External Program Memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to ExterE nal Data Memory A VPP External Access enable EA must be strapped to VSS in order to enable the 87C51 BH to fetch code from External Program Memory locations starting at 0000H up to FFFFH Note however that if either of the Lock Bits is programmed the logic level at EA is internally latched during reset E A must be strapped to VCC for internal program T execution his pin also receives the programming supply volta Xge (VPP) during EPROM programming XTAL1 Input to the inverting oscillator amplifier TAL2 Output from the inverting oscillator amplifier 2 Figure 4 External Clock Drive
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output respectively of an inverting amplifier which can be configured for use as an on-chip oscillator as shown in T Figure 3 Xo drive the device from an external clock source TAL1 should be driven while XTAL2 is left unconnected as shown in Figure 4 There are no requires ments on the duty cycle of the external clock signal ince the input to the internal clocking circuitry is through a divide-by-two flip-flop but minimum and maximum high and low times specified on the data A sheet must be observed n external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up This is due to interaction between the amplifier and its feedback capacitance Once the external signal meets the VIL and VIH specifications the capacitance will not exceed 20 pF 2
