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Part: 80C51GB-16
Category:
Microcontrollers
Description: CMOS 8-bit Microcontroller
Company: Intel Corporation
Datasheet: Download 80C51GB-16 datasheet File size : 1927 kB
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Datasheet text preview:
8XC51GB CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Commercial Express
87C51GB 8 Kbytes OTP 8 Kbytes Internal Program Memory 83C51GB 8 Kbytes Factory Programmable ROM 80C51GB CPU with RAM and I O 8XC51GB 3 5 MHz to 12 MHz g 20% VCC 8XC51GB-1 3 5 MHz to 16 MHz g 20% VCC
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8 Kbytes On-Chip ROM OTP ROM 256 Bytes of On-Chip Data RAM Two Programmable Counter Arrays wit2 h x 5 High Speed Input Output Channels Compare Capture Pulse Width Modulators Watchdog Timer Capabilities Three 16-Bit Timer Counters with C Four Programmable Modes apture Baud Rate Generation (Timer 2) Dedicated Watchdog Timer 8-Bit 8-Channel A D with E ight 8-Bit Result Registers Four Programmable Modes Programmable Serial Channel with F raming Error Detection Automatic Address Recognition Serial Expansion Port Programmable Clock Out ( Extended Temperature Range b 40 C to a 85 C)
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48 Programmable I O Lines with 40 Schmitt Trigger Inputs 15 7nterrupt Sources with I External 8 Internal Sources 4 Programmable Priority Levels Pre-Determined Port States on Reset High Performance CHMOS Process TTL and CHMOS Compatible Logic Levels Power Saving Modes 64K External Data Memory Space 64K External Program Memory Space Three Level Program Lock System ONCE (ON-Circuit Emulation) Mode Quick Pulse Programming Algorithm MCS 51 Microcontroller Fully Compatible Instruction Set Boolean Processor Oscillator Fail Detect Available in 68-Pin PLCC
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MEMORY ORGANIZATION
PROGRAM MEMORY Up to 8 Kbytes of the program memory can reside in the on-chip ROM Also the device D can address up to 64K of program memory external to the chip ATA MEMORY This microcontroller has a 256 x 8 on-chip RAM In addition it can address up to 64 Kbytes of T external data memory he Intel 8XC51GB is a single-chip control oriented microcontroller which is fabricated on Intel's CHMOS III-E technology The 8XC51GB is an enhanced version of the 8XC51FA and uses the same powerful instruction set and architecture as existing MCS 51 microcontroller products Added features make it an even more powerful microcontroller for applications that require On-Chip A D Pulse Width Modulation High Speed I O up down counting capabilities and memory protection features It also has a more versatile serial channel that facilitates multi-processor communications
I Other brands and names are the property of their respective owners nformation in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata N COPYRIGHT INTEL CORPORATION 1995 ovember 1994 Order Number 272337-002
8XC51GB
272337 1
Figure 1 8XC51GB Block Diagram
PROCESS INFORMATION
This device is manufactured on P629 0 a CHMOS III-E process Additional process and reliability information is available in Intel's Components Quality and Reliability Handbook Order No 210997
PACKAGES
Part 8XC51GB Prefix N Package Type 68-Pin PLCC
2
8XC51GB
PARALLEL I O PORTS
A The 8XC51GB contains six 8-bit parallel I O ports a ll six ports are bidirectional and consist of a latch n output driver and an input buffer Many of the P port pins have multiplexed I O and control functions
ort Pins as Inputs
The pins of all six ports are configured as inputs by writing a logic 1 to them Since Port 0 is an open S drain port it provides a very high input impedance ince pins of Port 1 2 3 4 and 5 have weak pullups (which are always on) they source a small current when driven low externally All ports except Port 0 P have Schmitt trigger inputs
ort Pins as Outputs
Port 0 has open drain outputs when it is not serving as the external data bus The internal pullup is active only when the pin is outputting a logic 1 during external memory access An external pullup resistor is required on Port 0 when it is serving as an output P port orts 1 2 3 4 and 5 have quasi-bidirectional outputs A strong pullup provides a fast rise time when the pin is set to a logic 1 This pullup turns on for two oscillator periods to drive the pin high and then turns W off The pin is held high by a weak pullup riting the P0 P1 P2 P3 P4 or P5 Special Function D Register sets the corresponding port pins All six port registers are bit addressable
ort States During Reset
Ports 0 and 3 reset asynchronously to a one and P Ports 1 2 4 and 5 reset to a zero asynchronously
IN DESCRIPTIONS
The 8XC51GB will be packaged in the 68-lead PLCC V package Its pin assignment is shown in Figure 2 VCC Supply Voltage
SS Circuit Ground
P 2
iagram is for Pin Reference Only Package Size is Not to Scale
OTP only
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Figure 2 Pin Connections 3
8XC51GB
ALTERNATE PORT FUNCTIONS
Ports 0 1 2 3 4 P nd 5 have alternate functions as well as their I O function as described below a ort Pin P0 0 ADO P0 7 AD7 P1 0 T2 P1 1 T2EX P1 2 ECI P1 3 CEXO P1 7 CEX4 P2 0 A8 P2 7 A15 P3 0 RXD P3 1 TXD P3 2 INT0 P3 3 INT1 P3 4 T0 P3 5 T1 P3 6 WR P3 7 RD P4 0 SEPCLK P4 1 SEPDAT P4 2 ECI1 P4 3 C1EX0 P4 7 C1EX4 P5 2 INT2 P5 6 INT6 RST Reset input A low on this pin for two machine cycles while the oscillator is running resets the device The port pins will be driven to their reset condition when a voltage below VIL max voltage is applied whether the oscillator is running or not An internal pullup resistor permits a power-on reset with o Anly a capacitor connected to VSS LE PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory This pin (ALE PROG) is also the program pulse input during programming of the I 87C51GB n normal operation ALE is emitted at a constant rate of the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped during each acI cess to external Data Memory f desired ALE operation can be disabled by setting bit 0 of SFR location 8EH With this bit set the pin is weakly pulled high However the ALE disable feature will be suspended during a MOVX or MOVC instruction idle mode power down mode and ICE mode The ALE disable feature will be terminated by re 4 set When the ALE disable feature is suspended or Alternate Function Multiplexed Address Data for External Memory Timer 2 External Clock Input Clock-Out Timer 2 Reload Capture Direction Control PCA External Clock Input PCA Capture Input Compare PWM Output High Byte of Address for External Memory Serial Port Input Serial Port Output External Interrupt 0 External Interrupt 1 Timer 0 External Clock Input Timer 1 External Clock Input Write Strobe for External Memory Read Strobe for External Memory Clock Source for Serial Expansion Port Data I O for the Serial Expansion Port PCA1 External Clock Input PCA1 Capture Input Compare PWM Output External Interrupt INT2 INT6 terminated the ALE pin will no longer be pulled up weakly Setting the ALE-disable bit has no affect if T the microcontroller is in external execution mode hroughout the remainder of this data sheet ALE will refer to the signal coming out of the ALE PROG pin and the pin will be referred to as the ALE PROG P pin SEN Program Store Enable is the read strobe to W external Program Memory hen the 8XC51GB is executing code from external Program Memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external Data MemoE ry A VPP External Access enable EA must be strapped to VSS in order to enable the device to fetch code from external Program Memory locations 0000H to 1FFFH Note however that if either of the Program Lock bits are programmed EA will be interE nally latched on reset A should be strapped to VCC for internal program executions
8XC51GB
This pin also receives the 12 75V programming supply voltage (VPP) during programming (OTP only) X XTAL1 Input to the inverting oscillator amplifier TAL2 Output from the inverting oscillator amplifiA er common timing reference Each Register Comparator Module is associated with a pin of Port 1 or Port 4 and is capable of performing input capture output compare and pulse width modulation functions The PCAs are exactly the same in function except for the T addition of clock input sources on PCA1 he PCA Counter and five Register Comparator C Modules each have a status bit in the CCON 1CON Special Function Registers These six status bits are set according to the selected modes of operation described below The CCON C1CON Register provides a convenient means to determine T which of the six PCA PCA1 interrupts has occurred he EC Bit in the IE (Interrupt Enable) Special Function Register is a global interrupt enable for the PCA 2
D CONVERTER
The 8XC51GB A D converter has a resolution of 8 bits and an accuracy of g 1 LSB ( g 2 LSB for channels 0 and 1) The conversion time for a single channel is 20 ms at a clock frequency of 16 MHz with the sample and hold function included Independent supply voltages are provided for the A D Also the T A D operates both in Normal Mode or in Idle Mode he A D has 8 analog input pins ACH0 (A D CHannel 0) ACH7 1 reference input pin COMPREF (COMParison REFerence) 1 control input pin TRIGIN (TRIGger IN) and 2 power pins AVREF (Voltage REFerence) and analog ground (ANalog GrouND) In addition the A D has 8 conversion reA sult registers ADRES0 (A D result for channel 0) DRES7 1 comparison result register ACMP (Analog Comparison) and 1 control register ACON (A D T Control) he control bit ACE (A D Conversion Enable) in ACON controls whether the A D is in operation or not ACE e 0 idles the A D ACE e 1 enables A D conversion The control bit AIM (A D Input mode) in ACON controls the mode of channel selection AIM e 0 is the Scan Mode and AIM e 1 is the Select Mode The result registers ADRES4 ADRES7 always contain the result of a conversion from the corresponding channels ACH4 CH7 However the result registers ADRES0 ADRES3 depend on the mode selected In the scan mode ADRES0 ADRES3 contain the values from ACH0 ACH3 In A the Select Mode one of the four channels ACH0 CH3 is converted four times and the four values are stored sequentially in locations ADRES0 ADRES3 Its channel is selected by bits ACS1 and ACS0 (A D Channel Select 1 and 0) in ACON P
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Figure 3 Programmable Counter Arrays
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output respectively of an inverting amplifier which can be configured for use as an on-chip oscillator as shown in Figure 4 Either a quartz crystal or ceramic resonator may be used More detailed information concerning the use of the on-chip oscillator is available in Application Note AP-155 ``Oscillators for Microcontrollers '' Order No 230659 X To drive the device from an external clock source TAL should be driven while XTAL2 floats as shown in Figure 5 There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a divide-by-two flip-flop but minimum and maximum high and low times specified on the data sheet must be observed 5
ROGRAMMABLE COUNTER ARRAYS
The Programmable Counter Arrays (PCA PCA1) are each made up of a Counter Module and five Register Comparator Modules as shown below The 16-bit output of the counter module is available to all five Register Comparator Modules providing one
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