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Part: 820
Category:
Interface and Interconnect
-> Chipsets
Description: 820 Chipset: 82820 Memory Controller Hub (MCH)
Company: Intel Corporation
Datasheet: Download 820 datasheet File size : 78 kB
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Intel® 820 Chipset Family: 82820 Memory Controller Hub (MCH)
Datasheet
July 2000
Order Number: 290630-002
Intel 82820 MCH
R
®
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel 82820 Memory Controller Hub (MCH) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation www.intel.com or call 1-800-548-4725 *Third-party brands and names are the property of their respective owners. Copyright © Intel Corporation 2000
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Datasheet
Intel 82820 MCH
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Contents
1. Overview....13 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.3. 2.4. Related Documents ............. 13 ® The Intel 820 Chipset System.....14 Intel 82820 MCH Overview ......... 16 Host Interface Signals ..........20 Direct RDRAM Interface Signals...22 The Hub Interface Signals ............ 22 AGP Interface Signals..........23 2.4.1. AGP Addressing Signals......23 2.4.2. AGP Flow Control Signals..........24 2.4.3. AGP Status Signals .... 24 2.4.4. AGP Clocking Signals (Strobes) ......... 25 2.4.5. AGP FRAME# Signals ......... 26 Clock and Reset Signals ...... 28 Voltage References, Power, Ground, and Test Signals ...... 29 Strap Signals.........29 Pin States During Reset.......30 Register Nomenclature and Access Attributes ..... 31 PCI Configuration Space Access .. 32 I/O Mapped Registers .......... 34 3.3.1. CONF_ADDRConfiguration Address Register ........ 34 3.3.2. CONF_DATAConfiguration Data Register ..... 35 Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0)...........36 3.4.1. VID--Vendor Identification Register (Device 0)..........38 3.4.2. DID--Device Identification Register (Device 0) .......... 38 3.4.3. PCICMD--PCI Command Register (Device 0)...........39 3.4.4. PCISTS--PCI Status Register (Device 0) ......... 40 3.4.5. RID--Revision Identification Register (Device 0) ....... 41 3.4.6. SUBC--Sub-Class Code Register (Device 0) ............ 41 3.4.7. BCC--Base Class Code Register (Device 0) .... 41 3.4.8. MLT--Master Latency Timer Register (Device 0) ...... 42 3.4.9. HDR--Header Type Register (Device 0) ..... 42 3.4.10. APBASE--Aperture Base Configuration Register (Device 0)....42 3.4.11. SVID--Subsystem Vendor ID Register (Device 0) ..... 44 3.4.12. SID--Subsystem ID Register (Device 0) ..... 44 3.4.13. CAPPTR--Capabilities Pointer Register (Device 0) ... 44 3.4.14. GAR0GAR7--RDRAM Group Architecture Register (Device 0) ..... 45 3.4.15. RDTR--RDRAM Timing Register (Device 0) .... 46 3.4.16. RDCR--RDRAM Control Register (Device 0) ............ 47 3.4.17. RDRR--RDRAM Refresh Register (Device 0) ........... 47 3.4.18. RPMR--RDRAM Power Management Register (Device 0).......48 3.4.19. FDHC--Fixed DRAM Hole Control Register (Device 0) ...... 49 3.4.20. PAM0PAM6--Programmable Attribute Map Registers (Device 0) .. 49 3.4.21. GBA0GBA7--RDRAM Group Boundary Address Register (Device 0).....53 3.4.22. DTC--DRAM Throttle Control Register (Device 0).....55
Signal Description.....19
2.5. 2.6. 2.7. 2.8. 3. 3.1. 3.2. 3.3.
Register Description .......... 31
3.4.
Datasheet
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Intel 82820 MCH
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3.5.
3.4.23. DRD--RDRAM Device Register Data Register (Device 0) ....... 56 3.4.24. RICM--RDRAM Initialization Control Management Register (Device 0) .... 57 3.4.25. 59 3.4.25. SMRAM--System Management RAM Control Register (Device 0) .. 59 3.4.26. ESMRAMC--Extended System Management RAM Control Register (Device 0) 60 3.4.27. ACAPID AGP Capability Identifier Register (Device 0).... 61 3.4.28. AGPSTAT--AGP Status Register (Device 0) ............ 62 3.4.29. AGPCMD--AGP Command Register (Device 0) ....... 63 3.4.30. AGPCTRL AGP Control Register (Device 0).......... 64 3.4.31. APSIZE Aperture Size Register (Device 0).... 65 3.4.32. ATTBASE--Aperture Translation Table Base Register (Device 0)... 66 3.4.33. AMTT--AGP Interface Multi-Transaction Timer Register (Device 0) ........ 66 3.4.34. LPTT--Low Priority Transaction Timer Register (Device 0) ..... 67 3.4.35. MCHCFG--MCH Configuration Register (Device 0).. 67 3.4.36. EAP--Error Address Pointer Register (Device 0) ...... 69 3.4.37. ERRSTS--Error Status Register (Device 0) ..... 70 3.4.38. ERRCMDError Command Register (Device 0) ...... 72 3.4.39. SMICMDSMI Command Register (Device 0) ......... 74 3.4.40. SCICMD--SCI Command Register (Device 0) .......... 75 3.4.41. SKPD--Scratchpad Data Register (Device 0) ........... 75 3.4.42. AGPBCTRL--AGP Buffer Control B Register (Device 0) ... 76 3.4.43. RTCE--RDRAM Temperature Calibration Enable Register (Device 0) ...... 76 3.4.44. AGPAPPEND--AGP Append Disable Register (Device 0)....... 76 AGP Bridge Registers (Device 1) .......... 77 3.5.1. VID1--Vendor Identification Register (Device 1) ....... 78 3.5.2. DID1--Device Identification Register (Device 1)........ 78 3.5.3. PCICMD1--PCI-PCI Command Register (Device 1) .......... 79 3.5.4. PCISTS1--PCI-PCI Status Register (Device 1)......... 80 3.5.5. RID1--Revision Identification Register (Device 1) ..... 81 3.5.6. SUBC1--Sub-Class Code Register (Device 1) .......... 81 3.5.7. BCC1--Base Class Code Register (Device 1)........... 81 3.5.8. MLT1--Master Latency Timer Register (Device 1) .... 82 3.5.9. HDR1--Header Type Register (Device 1)......... 82 3.5.10. PBUSN--Primary Bus Number Register (Device 1) .. 82 3.5.11. SBUSN--Secondary Bus Number Register (Device 1) ...... 83 3.5.12. SUBUSN--Subordinate Bus Number Register (Device 1).. 83 3.5.13. SMLT--Secondary Master Latency Timer Register (Device 1) ......... 84 3.5.14. IOBASE--I/O Base Address Register (Device 1) ...... 85 3.5.15. IOLIMIT--I/O Limit Address Register (Device 1) ....... 85 3.5.16. SSTS--Secondary PCI-PCI Status Register (Device 1) ..... 86 3.5.17. MBASE--Memory Base Address Register (Device 1) ........ 87 3.5.18. MLIMIT--Memory Limit Address Register (Device 1) ......... 87 3.5.19. PMBASE--Prefetchable Memory Base Address Register (Device 1) ........ 88 3.5.20. PMLIMIT--Prefetchable Memory Limit Address Register (Device 1) ......... 88 3.5.21. BCTRL--PCI-PCI Bridge Control Register (Device 1) ........ 89 3.5.22. ERRCMD1--Error Command Register (Device 1) .... 90
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Datasheet
Intel 82820 MCH
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4.
System Address Map.........91 4.1. Memory Address Ranges.....91 4.1.1. Compatibility Area ....... 92 4.1.2. Extended Memory Area ....... 95 4.1.3. AGP Memory Address Ranges...........97 4.1.4. AGP DRAM Graphics Aperture...........97 4.1.5. System Management Mode (SMM) Memory Range...98 4.1.6. Memory Shadowing .. 100 I/O Address Space ............. 100 MCH Decode Rules and Cross-Bridge Address Mapping .......... 102 4.3.1. The Hub Interface Decode Rules ..... 102 4.3.2. AGP Interface Decode Rules............102 4.3.3. Legacy VGA Ranges..........103 Host Interface......105 5.1.1. Host Addresses Above 4 GB ............ 107 5.1.2. Host Bus Cycles........107 5.1.3. Symmetric Multiprocessor (SMP) Protocol Support .......... 111 5.1.4. Frame Buffer Memory Support ......... 111 AGP Interface......112 5.2.1. AGP Target Operations ........... 112 5.2.2. AGP Transaction Ordering.......113 5.2.3. AGP Signal Levels .... 113 5.2.4. 4x AGP Protocol ....... 114 5.2.5. Fast Writes.......114 5.2.6. AGP Universal Connector........115 5.2.7. AGP FRAME# Transactions on AGP.........115 DRAM Interface...117 5.3.1. RDRAM............117 5.3.1.1. DRAM Organization, Configuration, and Speed....118 5.3.1.1.1. Rules for Populating RDRAM Devices......119 5.3.1.1.2. RDRAM CMOS Signals Description and Usage ......... 120 5.3.1.1.3. Direct RDRAM Core Refresh ..... 121 5.3.1.1.4. Direct RDRAM Current Calibration ..... 122 5.3.1.2. Direct RDRAM Command Encoding ............ 123 5.3.1.2.1. Row Packet (ROWA/ROWR).....123 5.3.1.2.2. Column Packet (COLC/COLX/COLM) ...... 124 5.3.1.2.3. Data Packet........126 5.3.1.3. Direct RDRAM Register Programming.........127 5.3.1.4. Direct RDRAM Operating States.........127 5.3.1.5. RDRAM Operating Pools ..... 128 5.3.1.6. RDRAM Power Management ........ 128 5.3.1.7. Data Integrity ......... 129 5.3.1.8. RDRAM Array Power Management .... 129 5.3.1.8.1. RDRAM On-die Internal Thermal Sensor Mechanism (Method 1) .......... 130 5.3.1.8.2. RDRAM Reads and Writes Counters/Timers Mechanism (Method 2) .......... 130 Power Management ........... 132 5.4.1. Processor Power State Control.........132 5.4.2. Sleep State Control ... 132 MCH Clocking ..... 133 5
4.2. 4.3.
5.
Functional Description ..... 105 5.1.
5.2.
5.3.
5.4.
5.5. Datasheet
Others parts begin by 82
82-1 82-2
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