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Part: 8207844PIN
Category:
Interface and Interconnect
-> Floppy Disk/IDE
Description: Chmos Single-chip Floppy Disk Controller
Company: Intel Corporation
Datasheet: Download 8207844PIN datasheet File size : 78 kB
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Datasheet text preview:
82078 44 PIN CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER
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Small Footprint and Low Height Package Enhanced Power Management Application Software Transparency Programmable Powerdown Command Save and Restore Commands for Zero-Volt Powerdown Auto Powerdown and Wakeup Modes Two External Power Management Pins Consumes No Power While in Powerdown Integrated Analog Data Separator 250 Kbps 300 Kbps 500 Kbps 1 Mbps Programmable Internal Oscillator Floppy Drive Support Features Drive Specification Command Selectable Boot Drive Standard IBM and ISO Format Features Format with Write Command for High Performance in Mass Floppy Duplication
Y
Y
Integrated Tape Drive Support 2 Standard 1 Mbps 500 Kbps 50 Kbps Tape Drives Perpendicular Recording Support for 4 MB Drives Integrated Host Disk Interface Drivers Fully Decoded Drive Select and Motor Signals Programmable Write Precompensation Delays S Addresses 256 Tracks Directly upports Unlimited Tracks 16 Byte FIFO Single-Chip Floppy Disk Controller Solution for Portables and Desktops 100% PC AT Compatible Fully Compatible with Intel386 TM SL Integrated Drive and Data Bus Buffers Separate 5 0V and 3 3V Versions of the 44 Pin part are Available Available in a 44 Pin QFP Package
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The 82078 a 24 MHz crystal a resistor package and a device chip select implements a complete solution All programmable options default to 82078 compatible values The dual PLL data separator has better performance than most board level discrete PLL implementations The FIFO allows better system performance in T multi-master (e g Microchannel EISA) he 82078 maintains complete software compatibility with the 82077SL 82077AA 8272A floppy disk controllers It contains programmable power management features while integrating all of the logic required for floppy T disk control The power management features are transparent to any application software he 82078 is fabricated with Intel's advanced CHMOS III technology and is also available in a 64-lead QFP pOckage a
ther brands and names are the property of their respective owners
I Other brands and names are the property of their respective owners nformation in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata D COPYRIGHT INTEL CORPORATION 1996 ecember 1995 Order Number 290474-003
82078 44 Pin CHMOS Single-Chip Floppy Disk Controller
CONTENTS
1 0 INTRODUCTION 2 0 MICROPROCESSOR INTERFACE 2 1 Status Data and Control Registers 2 1 1 Status Register B (SRB E REG EN e 1) 2 1 2 Digital Output Register (DOR) 2 1 3 Enhanced Tape Drive Register (TDR) 2 1 4 Datarate Select Register (DSR) 2 1 5 Main Status Register (MSR) 2 1 6 FIFO (DATA) 2 1 7 Digital Input Register (DIR) 2 2 Reset 2 2 1 Reset Pin (``HARDWARE'') Reset 2 2 2 DOR Reset vs DSR Reset (``SOFTWARE'' RESET) 2 3 DMA Transfers 3 0 DRIVE INTERFACE 3 1 Cable Interface 3 2 Host and FDD Interface Drivers 3 3 Data Separator 3 3 1 Jitter Tolerance 3 3 2 Locktime (tLOCK) 3 3 3 Capture Range 3 4 Write Precompensation PAGE
8 9 9 9 10 11 11 13 13 14 14 14 14 14 14 14 15 15 16 16 16 16
CONTENTS
4 0 POWER MANAGEMENT FEATURES 4 1 Power Management Scheme 4 2 Oscillator Power Management 4 3 Part Power Management 4 3 1 Direct Powerdown 4 3 2 Auto Powerdown 4 3 3 Wake Up Modes 4 3 3 1 Wake Up from DSR Powerdown 4 3 3 2 Wake Up from Auto Powerdown 4 4 Register Behavior 4 5 Pin Behavior 4 5 1 System Interface Pins 4 5 2 FDD Interface Pins 5 0 CONTROLLER PHASES 5 1 Command Phase 5 2 Execution Phase 5 2 1 Non-DMA Mode Transfers from the FIFO to the Host 5 2 2 Non-DMA Mode Transfers from the Host to the FIFO 5 2 3 DMA Mode Transfers from the FIFO to the Host 5 2 4 DMA Mode Transfers from the Host to the FIFO 5 2 5 Data Transfer Termination 5 3 Result Phase
PAGE
17 17 17 18 18 18 18 18 18 19 19 19 20 20 20 21 21 21 21 21 22 22
2
CONTENTS
6 0 COMMAND SET DESCRIPTIONS 6 1 Data Transfer Commands 6 1 1 Read Data 6 1 2 Read Deleted Data 6 1 3 Read Track 6 1 4 Write Data 6 1 5 Write Deleted Data 6 1 6 Verify 6 1 7 Format Track 6 1 7 1 Format Fields 6 2 Scan Commands 6 3 Control Commands 6 3 1 Read ID 6 3 2 Recalibrate 6 3 3 Drive Specification Command 6 3 4 Seek 6 3 5 Sense Interrupt Status 6 3 6 Sense Drive Status 6 3 7 Specify 6 3 8 Configure 6 3 9 Version 6 3 10 Relative Seek 6 3 11 DUMPREG 6 3 12 Perpendicular Mode Command 6 3 12 1 About Perpendicular Recording Mode 6 3 12 2 The Perpendicular Mode Command 6 3 13 Powerdown Mode Command 6 3 14 Part ID Command 6 3 15 Option Command 6 3 16 Save Command 6 3 17 Restore Command 6 3 18 Format and Write Command 6 3 19 Lock
PAGE
22 34 34 35 35 36 36 36 37 38 38 39 39 39 39 40 40 41 41 41 42 42 43 43 43 43 44 44 44 44 44 45 45
CONTENTS
7 0 STATUS REGISTER ENCODING 7 1 Status Register 0 7 2 Status Register 1 7 3 Status Register 2 7 4 Status Register 3 8 0 COMPATIBILITY 8 1 Compatibility with the FIFO 8 2 Drive Polling 9 0 PROGRAMMING GUIDELINES 9 1 Command and Result Phase Handshaking 9 2 Initialization 9 3 Recalibrates and Seeks 9 4 Read Write Data Operations 9 5 Formatting 9 6 Save and Restore 9 7 Verifies 9 8 Powerdown State and Recovery 9 8 1 Oscillator Power Management 9 8 2 Part Power Management 9 8 2 1 Powerdown Modes 9 8 2 2 Wake Up Modes
PAGE
46 46 46 47 47 48 48 48 48 49 49 51 51 53 54 55 55 55 55 55 56 56 56 58 59 59 62 62 62 63 64 70 71
10 0 DESIGN APPLICATIONS 10 1 Operating the 82078-3 in a 3 3V Design 10 2 Selectable Boot Drive 10 3 How to Disable the Native Floppy Contoller on the Motherboard 10 4 Replacing the 82077SL with a 82078 in a 5 0V Design 11 0 D C SPECIFICATIONS 11 1 Absolute Maximum Ratings 11 2 D C Characteristics 11 3 Oscillator 12 0 A C SPECIFICATIONS 12 1 Package Outline for the 44-Pin QFP Part 13 0 REVISION HISTORY
3
82078 44 PIN
290474 1
Figure 1-0 82078 44 Pin Pinout Table 1 0 82078 (44 Pin) Description Symbol Pin
IO
W Reset
H
Description
HOST INTERFACE RESET A A0 1 A2 34 40 39 38 I I NA NA RESET A high level places the 82078 in a known idle state All registers are cleared except those set by the Specify command ADDRESS Selects one of the host interface registers A2 A1 A0 Access Register 0 0 0 R Reserved 0 0 1 RW Status Register B 0 1 0 RW Digital Output Register 0 1 1 RW Tape Drive Register 1 0 0 R Main Status Register 1 1 1 1 1 CS
R 41 42
SRB DOR TDR MSR DSR FIFO DIR CCR
0 0 1 1 1
0 1 0 1 1
W RW Reserved R W
Data Rate Select Register Data Register (FIFO) Digital Input Register Configuration Control Register
I I
NA NA
a CHIP SELECT Decodes the base address range and qualifies RD nd WR
D 4
READ Read control signal for data transfers from the floppy drive to the system
82078 44 PIN
Table 1 0 82078 (44 Pin) Description (Continued) Symbol Pin
IO
HW Reset
Description
HOST INTERFACE (Continued) WR D RQ D ACK D DB0 B1 DB2 DB3 DB4 DB5 DB6 DB7 INT T C X 1 X2 36 35 NA 13 I NA 2 3 4 5 8 9 10 11 12 IO
1 43
I O
NA
WRITE Write control signal for data transfers to the floppy drive from the system DMA REQUEST Requests service from a DMA controller N ormally active high but will go to high impedance in AT and Model 30 modes when the appropriate bit is set in the DOR
44
I
NA
W DMA ACKNOWLEDGE Control input that qualifies the RD R inputs in DMA cycles Normally active low but is disabled in AT and Model 30 modes when the appropriate bit is set in the DOR
DATA BUS 12 mA data bus
O
INTERRUPT Signals a data transfer in non-DMA mode and when status is valid Normally active high but goes to high impedance when the appropriate bit is set in the DOR TERMINAL COUNT Control line from a DMA controller that terminates the current disk transfer TC is effective only when qualified by DACK This input is active high EXTERNAL CLOCK OR CRYSTAL Connection for a 24 MHz fundamental mode parallel resonant crystal X1 can also be driven by an external clock (external oscillator) which can be either at 48 MHz or 24 MHz If external oscillator is used then the PDOSC bit can be set to turn off the internal oscillator Also if a 48 MHz external oscillator is used then the CLK48 bit must be set in the enhanced CONFIGURE command
P LL SECTION D RDDATA ISK CONTROL TRK0 I NDX W P D SKCHG D RVDEN0 DRVDEN1 WRDATA 21 22
23 19 14 15 16 20
I
NA
READ DATA Serial data from the floppy disk
I I I I O O
NA NA NA NA
TRACK0 This is an active low signal that indicates that the head on track 0 INDEX This is an active low signal that indicates the beginning of the track WRITE PROTECT This is an active low signal that indicates whether the floppy disk in the drive is write protected DISK CHANGE This is an input from the floppy drive reflected in the DIR DRIVE DENSITY These signals are used by the floppy drive to configure the drive for the appropriate media WRITE DATA MFM serial data to the drive Precompensation value is selectable through software 5
Others parts begin by 82
82-1 82-2
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