Datasheet text preview:
82078 64 PIN CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER
Y
Small Footprint and Low Height Packages Supports Standard 5 0V as well as Low Voltage 3 3V Platforms Selectable 3 3V and 5 0V Configuration 5 0V Tolerant Drive Interface Enhanced Power Management Application Software Transparency Programmable Powerdown Command Save and Restore Commands for Zero-Volt Powerdown Auto Powerdown and Wakeup Modes Two External Power Management Pins Consumes no Power when in Powerdown Integrated Analog Data Separator 250 Kbps 300 Kbps 500 Kbps 1 Mbps 2 Mbps Programmable Internal Oscillator Floppy Drive Support Features Drive Specification Command Media ID Capability Provides Media Recognition Drive ID Capability Allows the User to Recognize the Type of Drive
Y
Selectable Boot Drive Standard IBM and ISO Format Features Format with Write Command for High Performance in Mass Floppy Duplication
Y
Y
Integrated Tape Drive Support 2 Standard 1 Mbps 500 Kbps 50 Kbps Tape Drives New 2 Mbps Tape Drive Mode Perpendicular Recording Support for 4 MB Drives Integrated Host Disk Interface Drivers Fully Decoded Drive Select and Motor Signals Programmable Write Precompensation Delays S Addresses 256 Tracks Directly upports Unlimited Tracks 16 Byte FIFO Single-Chip Floppy Disk Controller Solution for Portables and Desktops 100% PC AT Compatible 100% PS 2 Compatible 100% PS 2 Model 30 Compatible Fully Compatible with Intel386 TM SL Microprocessor SuperSet Integrated Drive and Data Bus Buffers Available in 64 Pin QFP Package
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Y Y
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Y
Y
Y Y
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Y Y
The 82078 a 24 MHz crystal a resistor package and a device chip select implements a complete solution All programmable options default to 82078 compatible values The dual PLL data separator has better performance than most board level discrete PLL implementations The FIFO allows better system performance in T multi-master (e g Microchannel EISA) he 82078 maintains complete software compatibility with the 82077SL 82077AA 8272A floppy disk controllers It contains programmable power management features while integrating all of the logic required for floppy disk control The power management features are transparent to any application software There are two T versions of 82078 floppy disk controllers the 82078SL and 82078-1 he 82078 is fabricated with Intel's advanced CHMOS III technology and is also available in a 44-lead QFP pOckage a
ther brands and names are the property of their respective owner
I Other brands and names are the property of their respective owners nformation in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata O COPYRIGHT INTEL CORPORATION 1996 ctober 1995 Order Number 290475-004
82078 64 Pin CHMOS Single-Chip Floppy Disk Controller
CONTENTS
1 0 INTRODUCTION 2 0 MICROPROCESSOR INTERFACE 2 1 Status Data and Control Registers 2 1 1 Status Register A (SRA PS 2 Mode) 2 1 2 Status Register A (SRA M odel 30 Mode) 2 1 3 Status Register B (SRB E nhanced AT EISA) 2 1 4 Status Register B (SRB PS 2 Mode) 2 1 5 Status Register B (SRB M odel 30 Mode) 2 1 6 Digital Output Register (DOR) 2 1 7 Tape Drive Register (TDR AT EISA PS 2 Model 30) 2 1 8 Enhanced Tape Drive Register (TDR AT PS 2 Model 30 EREG EN e 1) 2 1 9 Datarate Select Register (DSR) 2 1 10 Main Status Register (MSR) 2 1 11 FIFO (DATA) 2 1 12 Digital Input Register (DIR P C-AT MODE) 2 1 13 Digital Input Register (DIR P S 2 MODE) 2 1 14 Digital Input Register (DIR M ODEL 30 MODE) 2 1 15 Configuration Control Register (CCR PS 2 MODES) 2 1 16 Configuration Control Register (CCR MODEL 30 MODE) 2 2 Reset 2 2 1 Reset Pin (``HARDWARE'') Reset 2 2 2 DOR Reset vs DSR Reset (``SOFTWARE'' RESET) 2 3 DMA Transfers PAGE
8 9 9 9 10 10 11 11 11 12
CONTENTS
3 0 DRIVE INTERFACE 3 1 Cable Interface 3 2 Data Separator 3 2 1 Jitter Tolerance 3 2 2 Locktime (tLOCK) 3 2 3 Capture Range 3 3 Write Precompensation 4 0 POWER MANAGEMENT FEATURES 4 1 Power Management Scheme 4 2 3 3V Support for Portable Platforms 4 3 Oscillator Power Management 4 4 Part Power Management 4 4 1 Direct Powerdown 4 4 2 Auto Powerdown 4 4 3 Wake Up Modes 4 4 3 1 Wake Up from DSR Powerdown 4 4 3 2 Wake Up from Auto Powerdown 4 5 Register Behavior 4 6 Pin Behavior 4 6 1 System Interface Pins 4 6 2 FDD Interface Pins 5 0 CONTROLLER PHASES 5 1 Command Phase 5 2 Execution Phase 5 2 1 Non-DMA Mode Transfers from the FIFO to the Host 5 2 2 Non-DMA Mode Transfers from the Host to the FIFO 5 2 3 DMA Mode Transfers from the FIFO to the Host 5 2 4 DMA Mode Transfers from the Host to the FIFO 5 2 5 Data Transfer Termination 5 3 Result Phase
CONTENTS
7 0 STATUS REGISTER ENCODING 7 1 Status Register 0 7 2 Status Register 1 7 3 Status Register 2 7 4 Status Register 3 8 0 COMPATIBILITY 8 1 PS 2 vs AT vs Model 30 Mode 8 2 Compatibility with the FIFO 8 3 Drive Polling 9 0 PROGRAMMING GUIDELINES 9 1 Command and Result Phase Handshaking 9 2 Initialization 9 3 Recalibrates and Seeks 9 4 Read Write Data Operations 9 5 Formatting 9 6 Save and Restore 9 7 Verifies 9 8 Powerdown State and Recovery 9 8 1 Oscillator Power Management 9 8 2 Part Power Management 9 8 2 1 Powerdown Modes 9 8 2 2 Wake Up Modes
10 0 DESIGN APPLICATIONS 10 1 Operating the 82078SL in a 3 3V Design 10 2 Selectable Boot Drive 10 3 How to Disable the Native Floppy Controller on the Motherboard 10 4 Replacing the 82077SL with an 82078 in a 5 0V Design 11 0 D C SPECIFICATIONS 11 1 Absolute Maximum Ratings 11 2 D C Characteristics 11 3 Oscillator 12 0 A C SPECIFICATIONS 12 1 Package Outline for the 64 QFP Part 13 0 REVISION HISTORY
82078 64 PIN
290475 1
Figure 1-0 82078 Pinout Table 1-0 82078 (64 Pin) Description Symbol Pin IO
H
W
Reset
Description
HOST INTERFACE RESET A A0 1 A2 50 58 57 55 I I NA NA RESET A high level places the 82078 in a known idle state All registers are cleared except those set by the Specify command ADDRESS Selects one of the host interface registers A2 A1 A0 Access Register 0 0 0R Status Register A 0 0 1 RW Status Register B 0 1 0 RW Digital Output Register 0 1 1 RW Tape Drive Register 1 0 0R Main Status Register 1 0 0W Data Rate Select Register 1 0 1 RW Data Register (FIFO) 1 1 0 Reserved 1 1 1R Digital Input Register 1 1 1W Configuration Control Register
SRA SRB DOR TDR MSR DSR FIFO DIR CCR
and
CS
4
60
I
NA
CHIP SELECT Decodes the base address range and qualifies RD WR
82078 64 PIN
Table 1-0 82078 (64 Pin) Description (Continued) Symbol Pin IO
H
W
Reset
Description
HOST INTERFACE (Continued) RD W R D RQ D ACK D DB0 B1 DB2 DB3 DB4 DB5 DB6 DB7 IDENT0 IDENT1 2 4 5 7 10 12 13 15 6 11 IO
1 61 63
I I O
NA NA
READ Read control signal for data transfers from the floppy drive to the system WRITE Write control signal for data transfers to the floppy drive from the system DMA REQUEST Requests service from a DMA controller Normally active high but will go to high impedance in AT and Model 30 modes when the appropriate bit is set in the DOR
64
I
NA
DMA ACKNOWLEDGE Control input that qualifies the RD WR inputs in DMA cycles Normally active low but is disabled in AT and Model 30 modes when the appropriate bit is set in the DOR DATA BUS 12 mA data bus
I
NA
IDENTITY These inputs decode between the several operation modes available to the user These pins have no effect on the DRVDEN pins IDENT0 IDENT1 INTERFACE 1 1 AT mode 1 0 ILLEGAL 0 1 PS 2 mode 0 0 Model 30 S AT MODE Major options are enables DMA gate logic TC is active high Ptatus Register B is available based on a bit the powerdown command S 2 MODE Major options are no DMA gate logic TC is active low Status M Registers A B are available ODEL 30 MODE Major options are enable DMA gate logic TC is active high Status Registers A B are available
I NT T C X 1 X2 52 51 NA 18 I NA 17 O
INTERRUPT Signals a data transfer in non-DMA mode and when status is valid Normally active high but goes to high impedance when the appropriate bit is set in the DOR TERMINAL COUNT Control line from a DMA controller that terminates the current disk transfer TC is effective only when qualified by DACK This input is active high in the AT and Model 30 modes when the appropriate bit is set in the DOR EXTERNAL CLOCK OR CRYSTAL Connection for a 24 MHz fundamental mode parallel resonant crystal X1 can also be driven by an external clock (external oscillator) which can be either at 48 MHz or 24 MHz If external oscillator is used then the PDOSC bit can be set to turn off the internal oscillator Also if a 48 MHz exernal oscillator is used then the CLK48 bit must be set in the enhanced CONFIGURE command 5
