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Details, datasheet, quote on part number:82C54
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Datasheet text preview:
82C54 CHMOS PROGRAMMABLE INTERVAL TIMER
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Compatible with all Intel and most other microprocessors High Speed ``Zero Wait State'' Operation with 8 MHz 8086 88 and 80186 188 Handles Inputs from DC 10 MHz for 82C54-2 Available in EXPRESS Standard Temperature Range Extended Temperature Range
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Three independent 16-bit counters Low Power CHMOS 8 MHz Count ICC e 10 mA frequency Completely TTL Compatible Six Programmable Counter Modes Binary or BCD counting Status Read Back Command Available in 24-Pin DIP and 28-Pin PLCC
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Y Y Y
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The Intel 82C54 is a high-performance CHMOS version of the industry standard 8254 counter timer which is designed to solve the timing control problems common in microcomputer system design It provides three independent 16-bit counters each capable of handling clock inputs up to 10 MHz All modes are software S programmable The 82C54 is pin compatible with the HMOS 8254 and is a superset of the 8253 p ix programmable timer modes allow the 82C54 to be used as an event counter elapsed time indicator Trogrammable one-shot and in many other applications he 82C54 is fabricated on Intel's advanced CHMOS III technology which provides low power consumption with performance equal to or greater than the equivalent HMOS product The 82C54 is available in 24-pin DIP and 28-pin plastic leaded chip carrier (PLCC) packages 2
231244 3 PLASTIC LEADED CHIP CARRIER
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Figure 1 82C54 Block Diagram
231244 2 Diagrams are for pin reference only P F ackage sizes are not to scale
igure 2 82C54 Pinout
October 1994
Order Number 231244-006
82C54
Table 1 Pin Description Symbol DIP D7-D0 C OLK 0 GUT 0 GATE 0 OND GUT 1 C ATE 1 GLK 1 OATE 2 C UT 2 ALK 2 1 A0 1-8 9 10 11 12 13 14 15 16 17 18 20-19 Pin Number PLCC 2-9 10 12 13 14 16 17 18 19 20 21 23-22 IO I O I O I I I O I I c ata Bidirectional tri-state data bus lines D onnected to system data bus Clock 0 Clock input of Counter 0 Output 0 Output of Counter 0 Gate 0 Gate input of Counter 0 Ground Power supply connection Out 1 Output of Counter 1 Gate 1 Gate input of Counter 1 Clock 1 Clock input of Counter 1 Gate 2 Gate input of Counter 2 Out 2 Output of Counter 2 Clock 2 Clock input of Counter 2 Address Used to select one of the three Counters or the Control Word Register for read or write operations Normally connected to the system addA ss bus re
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Type
Function
A0 0 1 0 1
Selects Counter 0 Counter 1 Counter 2 Control Word Register
0 0 1 1 CS R D W R V NCC C 24 28 1 11 15 25 22 23 26 27 I I 21 24 I
Chip Select A low on this input enables the 82C54 to respond to RD and WR signals RD and WR are ignored otherwise Read Control This input is low during CPU read operations Write Control This input is low during CPU write operations Power a5V power supply connection No Connect sired delay After the desired delay the 82C54 will interrupt the CPU Software overhead is minimal and S variable length delays can easily be accommodated ome of the other counter timer functions common to microcomputers which can be implemented with the 82C54 are
FUNCTIONAL DESCRIPTION General
The 82C54 is a programmable interval timer counter I designed for use with Intel microcomputer systems t is a general purpose multi-timing element that can be treated as an array of I O ports in the system T software he 82C54 solves one of the most common problems in any microcomputer system the generation of accurate time delays under software control Instead of setting up timing loops in software the programmer configures the 82C54 to match his requirements and programs one of the counters for the de2
Real time clock Even counter Digital one-shot Programmable rate generator Square wave generator Binary rate multiplier Complex waveform generator Complex motor controller
82C54
Block Diagram
DATA BUS BUFFER This 3-state bi-directional 8-bit buffer is used to interface the 82C54 to the system bus (see Figure 3) 2
ONTROL WORD REGISTER The Control Word Register (see Figure 4) is selected by the Read Write Logic when A1 A0 e 11 If the CPU then does a write operation to the 82C54 the data is stored in the Control Word Register and is interpreted as a Control Word used to define the T operation of the Counters s he Control Word Register can only be written to tatus information is available with the Read-Back Command 2
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Figure 3 Block Diagram Showing Data Bus Buffer and Read Write Logic Functions
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READ WRITE LOGIC The Read Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the 82C54 A1 and A0 select one of the three counters or the Control Word Register to be read from written into A ``low'' on the RD input tells the 82C54 that the CPU is reading one of the counters A ``low'' on the WR input tells the 82C54 that the CPU is writing either a Control Word or an initial count Both RD and WR are qualified by CS RD and WR are ignored unless the 82C54 has b Teen selected by holding CS low The WR and CLK signals should be synchronous his is accomplished by using a CLK input signal to the 82C54 counters which is a derivative of the system clock source Another technique is to externally synchronize the WR and CLK input signals This is done by gating WR with CLK Figure 4 Block Diagram Showing Control Word Register and Counter Functions COUNTER 0 COUNTER 1 COUNTER 2 These three functional blocks are identical in operation so only a single Counter will be described The internal block diagram of a single counter is shown T in Figure 5 he Counters are fully independent Each Counter T may operate in a different Mode he Control Word Register is shown in the figure it is not part of the Counter itself but its contents determine how the Counter operates 3 C
82C54
stored in the CR and later transferred to the CE The Control Logic allows one register at a time to be loaded from the internal bus Both bytes are transferred to the CE simultaneously CRM and CRL are cleared when the Counter is programmed In this way if the Counter has been programmed for one byte counts (either most significant byte only or least N significant byte only) the other byte will be zero ote that the CE cannot be written into whenever a T count is written it is written into the CR he Control Logic is also shown in the diagram CLK n GATE n and OUT n are all connected to the out8ide world through the Control Logic s
2C54 SYSTEM INTERFACE
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Figure 5 Internal Block Diagram of a Counter The status register shown in the Figure when latched contains the current contents of the Control Word Register and status of the output and null count flag (See detailed explanation of the ReadBack command ) The actual counter is labelled CE (for ``Counting Element'') It is a 16-bit presettable synchronous down O counter LM and OLL are two 8-bit latches OL stands for ``Output Latch'' the subscripts M and L stand for ``Most significant byte'' and ``Least significant byte'' respectively Both are normally referred to as one unit and called just OL These latches normally ``follow'' the CE but if a suitable Counter Latch Command is sent to the 82C54 the latches ``latch'' the present count until read by the CPU and then return to ``following'' the CE One latch at a time is enabled by the counter's Control Logic to drive the internal bus This is how the 16-bit Counter communicates over the 8-bit internal bus Note that the CE itself cannot be read whenever you read the count it is S the OL that is being read imilarly there are two 8-bit registers called CRM and CRL (for ``Count Register'') Both are normally referred to as one unit and called just CR When a new count is written to the Counter the count is
The 82C54 is treated by the systems software as an array of peripheral I O ports three are counters and the fourth is a control register for MODE programB ming Aasically the select inputs A0 A1 connect to the A0 1 address bus signals of the CPU The CS can be derived directly from the address bus using a linear select method Or it can be connected to the output of a decoder such as an Intel 8205 for larger systems 2
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Figure 6 82C54 System Interface
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82C54
OPERATIONAL DESCRIPTION General
T After power-up the state of the 82C54 is undefined he Mode count value and output of all Counters H are undefined ow each Counter operates is determined when it is programmed Each Counter must be programmed before it can be used Unused counters need not be programmed
rogramming the 82C54
Counters are programmed by writing a Control Word and then an initial count The control word format is A shown in Figure 7 ll Control Words are written into the Control Word Register which is selected when A1 A0 e 11 The Control Word itself specifies which Counter is being B programmed y contrast initial counts are written into the CounP rs not the Control Word Register The A1 A0 inte puts are used to select the Counter to be written into The format of the initial count is determined by the Control Word used
C
ontrol Word Format
A1 A0 e 11 CS e 0 RD e 1 WR e 0 D7 SC1 SC S Select Counter C1 SC0 0 0 1 1 0 1 0 1 Select Counter 0 Select Counter 1 Select Counter 2 Read-Back Command (See Read Operations) D6 SC0 D5 RW1 D4 RW0 D3 M2 D2 M1 D1 M0 D0 BCD
MODE M2 0 0 X X 1 1 BC0 D
M1 0 0 1 1 0 0
M0 0 1 0 1 0 1 Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5
RW R Read Write W1 RW0 0 1 0 1 N 0 1 0 1 Counter Latch Command (see Read Operations) Read Write least significant byte only Read Write most significant byte only Read Write least significant byte first t hen most significant byte
M
Binary Counter 16-bits 1 Binary Coded Decimal (BCD) Counter (4 Decades)
OTE Don't care bits (X) should be 0 to insure compatibility with future Intel products
Figure 7 Control Word Format
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