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Details, datasheet, quote on part number:830
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| Part: | 830 |
| Category: | Interface and Interconnect => Chipsets |
| Description: | Intel 830 Chipset Family: 82830 Graphics And Memory Controller Hub (GMCH-M) |
| Company: | Intel Corporation |
| Datasheet: | Download 830 datasheet File size : 2016 kB |
| Request For quote: | Find where to buy 830
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Datasheet text preview:
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Intel® 830 Chipset Family: 82830 Graphics and Memory Controller Hub (GMCH-M)
Datasheet
January 2002
Order Number: 298338-003
Intel 830 Chipset Family
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. The information provided in this report, and related materials and presentations, are intended to illustrate the effects of certain design variables as determined by modeling, and are neither a recommendation nor endorsement of any specific system-level design practices or targets. The model results are based on a simulated notebook configuration, and do not describe or characterize the properties of any specific, existing system design. A detailed description of the simulated notebook configuration is available upon request. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 830 Graphics-Memory Controller Hub- Mobile (GMCH-M) product may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. I2C is a two-wire communications bus/protocol developed by Philips*. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Intel® , Pentium®, Celeron®, and SpeedStepTM are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and other countries. *Other brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copyright © Intel Corporation 2002
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Datasheet
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Intel 830 Chipset Family
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Contents
1 2 Introduction .............. 24 1.1 Document References......... 24 Overview ... 25 2.1 Terminology.......... 28 2.2 Intel 830 Chipset Family System Architecture ..... 29 2.2.1 Intel 830MP Chipset... 29 2.2.2 Intel 830M Chipset ..... 29 2.2.3 Intel 830MG Chipset .. 29 2.3 Intel 830 Chipset Family Host Interface ...... 30 2.4 Intel 830 Chipset Family System Memory Interface ..... 30 2.5 Intel 830M / 830MP Discrete AGP Interface ........ 30 2.6 Intel 830M / 830MG Internal Graphics Introduction ...... 31 2.7 Intel 830M / 830MG Internal Graphics Display Interface .... 31 2.7.1 Intel 830M and 830MG Analog Display Port..... 31 2.7.2 Intel 830M and 830MG DVO interfaces ...... 31 2.7.2.1 Intel 830M and 830MG Dedicated DVOA Interface ..... 32 2.7.2.2 Intel 830M and 830MG DVOB and DVOC Interfaces ........... 32 Signal Description .... 33 3.1 Common Signals for the Intel 830 Chipset Family........ 35 3.1.1 Host Interface Signals ......... 35 3.1.2 System Memory Interface ......... 37 3.1.3 Hub Interface Signals.......... 38 3.1.4 Clocking and Reset .... 38 3.1.5 Reserved Signals ....... 39 3.2 Common Signals for 830M and 830MP Chipset Discrete AGP Graphics Implementation ..... 40 3.2.1 AGP Addressing Signals........... 40 3.2.2 AGP Flow Control Signals......... 41 3.2.3 AGP Status Signals.... 41 3.2.4 AGP Clocking Signals Strobes ....... 42 3.2.5 PCI Signals - AGP Semantics........... 43 3.2.6 PCI Pins During PCI Transactions on AGP Interface ......... 44 3.3 Common Signals for 830M and 830MG Chipset Internal Graphics Implementation .... 45 3.3.1 Dedicated Digital Video Port (DVOA) ......... 46 3.3.2 Multiplexed Digital Video Port B (DVOB) .... 48 3.3.3 Multiplexed Digital Video Port (DVOC) ....... 50 3.3.3.1 DVOBC to AGP Pin Mapping ......... 51 3.3.3.2 DVO Miscellaneous Signals .. 51 3.3.4 Analog Display ........... 52 3.3.5 Display Control Signals ....... 53 3.3.5.1 DVO Display Control Signals ......... 54 3.3.5.2 Display Control Signals to AGP Pin Mapping ........ 54 3.4 Intel 830 Chipset Family Voltage References, PLL Power .......... 55 3.5 Intel 830 Chipset Family Strap Signals ....... 56 Register Description.......... 57 4.1 Conceptual Overview of the Platform Configuration Structure .... 57 4.2 Routing Configuration Accesses to PCI0 or AGP/PCI ........ 59
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4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.3 4.4
4.5
Intel 830 Chipset Family GMCH-M Configuration Cycle Flow Charts.........60 PCI Bus Configuration Mechanism.....60 PCI Bus #0 Configuration Mechanism.........61 Primary PCI and Downstream Configuration Mechanism ... 61 Intel 830M and 830MP Chipset AGP/PCI1 Bus Configuration Mechanism 62 Intel 830 Chipset Family Internal GMCH-M Configuration Register Access Mechanism ........ 64 Intel 830 Chipset Family GMCH-M Register Introduction ............ 64 Intel 830 Chipset Family I/O Mapped Registers ... 65 4.4.1 CONFIG_ADDRESS - Configuration Address Register......66 4.4.2 CONFIG_DATA - Configuration Data Register .......... 68 Intel 830 Chipset Family GMCH-M Internal Device Registers ..... 68 4.5.1 SDRAM Controller/Host-hub Interface Device Registers - Device #0.........69 4.5.1.1 VID - Vendor Identification Register - Device #0 .... 71 4.5.1.2 DID - Device Identification Register - Device #0.....71 4.5.1.3 PCICMD - PCI Command Register - Device #0 ..... 72 4.5.1.4 PCISTS - PCI Status Register - Device #0....73 4.5.1.5 RID - Revision Identification Register - Device #0..74 4.5.1.6 SUBC - Sub-Class Code Register - Device #0.......74 4.5.1.7 BCC - Base Class Code Register - Device #0........75 4.5.1.8 MLT - Master Latency Timer Register - Device #0 ....... 75 4.5.1.9 HDR - Header Type Register - Device #0 ..... 75 4.5.1.10 APBASE - Aperture Base Configuration Register - Device #0 ...... 76 4.5.1.11 SVID - Subsystem Vendor ID - Device #0 .... 77 4.5.1.12 SID - Subsystem ID - Device #0 .... 77 4.5.1.13 CAPPTR - Capabilities Pointer - Device #0..77 4.5.1.14 RRBAR - Register Range Base Address Register - Device #0......78 4.5.1.15 GCC0 - GMCH Control Register #0 - Device #0 .... 79 4.5.1.16 GCC1-GMCH Control Register #1 - Device #0 .... 81 4.5.1.17 FDHC - Fixed DRAM Hole Control Register - Device #0 ...... 84 4.5.1.18 PAM(6:0) - Programmable Attribute Map Registers - Device #0....85 4.5.1.19 DRB -- DRAM Row Boundary Register - Device #0....88 4.5.1.20 DRA -- DRAM Row Attribute Register - Device #0......89 4.5.1.21 DRT--DRAM Timing Register - Device #0....90 4.5.1.22 DRC - DRAM Controller Mode Register - Device #0 .... 92 4.5.1.23 DTC - DRAM Throttling Control Register - Device #0. .......... 94 4.5.1.24 SMRAM - System Management RAM Control Register Device #0 ....... 96 4.5.1.25 ESMRAMC - Extended System Management RAM Control Register - Device #0 ..... 97 4.5.1.26 ERRSTS Error Status Register Device #0........98 4.5.1.27 ERRCMD - Error Command Register - Device #0..99 4.5.1.28 ACAPID - AGP Capability Identifier Register - Device #0 ... 101 4.5.1.29 AGPSTAT - AGP Status Register - Device #0 ..... 102 4.5.1.30 AGPCMD - AGP Command Register - Device #0 ...... 103 4.5.1.31 AGPCTRL - AGP Control Register - Device #0....104 4.5.1.32 AFT AGP Functional Test Register Device #0 ..... 104 4.5.1.33 APSIZE Aperture Size - Device #0 .......... 105 4.5.1.34 ATTBASE Aperture Translation Table Base Register Device #0 ..... 106 4.5.1.35 AMTTAGP Interface Multi-Transaction Timer Register - Device #0 .......106 4.5.1.36 LPTTLow Priority Transaction Timer Register - Device #0.......107
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4.5.1.37 4.5.2
4.5.3
BUFF_SC System Memory Buffer Strength Control Register Device #0..... 108 4.5.1.37.1 SDR Drive Strength Register Description ......... 108 830M and 830MP Chipset HOST-AGP Bridge Registers - Device #1 ..... 111 4.5.2.1 VID1 - Vendor Identification Register - Device #1...... 112 4.5.2.2 DID1 - Device Identification Register - Device #1 ...... 112 4.5.2.3 PCICMD1 - PCI-PCI Command Register - Device #1 ........ 113 4.5.2.4 PCISTS1 - PCI-PCI Status Register - Device #1 ....... 114 4.5.2.5 RID1 - Revision Identification Register - Device #1 ............ 115 4.5.2.6 SUBC1 - Sub-Class Code Register - Device #1 .. 115 4.5.2.7 BCC1 - Base Class Code Register - Device #1 ... 116 4.5.2.8 MLT1 - Master Latency Timer Register - Device #1 ........... 116 4.5.2.9 HDR1 - Header Type Register - Device #1 .......... 117 4.5.2.10 PBUSN - Primary Bus Number Register - Device #1.......... 117 4.5.2.11 SBUSN - Secondary Bus Number Register - Device #1.... 117 4.5.2.12 SUBUSN - Subordinate Bus Number Register - Device #1 ......... 118 4.5.2.13 SMLT - Secondary Master Latency Timer Register - Device #1.. 118 4.5.2.14 IOBASE - I/O Base Address Register - Device #1..... 119 4.5.2.15 IOLIMIT - I/O Limit Address Register - Device #1...... 119 4.5.2.16 SSTS - Secondary PCI-PCI Status Register - Device #1 .. 120 4.5.2.17 MBASE - Memory Base Address Register - Device #1 ...... 121 4.5.2.18 MLIMIT - Memory Limit Address Register - Device #1 ....... 121 4.5.2.19 PMBASE - Prefetchable Memory Base Address Register - Device #1 ...... 122 4.5.2.20 PMLIMIT - Prefetchable Memory Limit Address Register - Device #1 ...... 123 4.5.2.21 BCTRL - PCI-PCI Bridge Control Register - Device #1 ...... 124 4.5.2.22 ERRCMD1 - Error Command Register - Device #1 ........... 125 830M and 830MG Chipset Integrated Graphics Device Registers Device #2 ........ 126 4.5.3.1 VID2 - Vendor Identification Register Device #2..... 127 4.5.3.2 DID2 - Device Identification Register - Device #2 ...... 128 4.5.3.3 PCICMD2 - PCI Command Register - Device #2....... 128 4.5.3.4 PCISTS2 - PCI Status Register - Device #2 ........ 130 4.5.3.5 RID2 - Revision Identification Register - Device #2 ............ 131 4.5.3.6 CC - Class Code Register - Device #2........ 131 4.5.3.7 CLS - Cache Line Size Register - Device #2 ....... 132 4.5.3.8 MLT2 - Master Latency Timer Register - Device #2 ........... 132 4.5.3.9 HDR2 - Header Type Register - Device #2 .......... 132 4.5.3.10 GMADR - Graphics Memory Range Address Register Device #2 ...... 133 4.5.3.11 MMADR - Memory Mapped Range Address Register Device #2 ...... 134 4.5.3.12 SVID2 - Subsystem Vendor Identification Register - Device #2 .. 134 4.5.3.13 SID2 - Subsystem Identification Register - Device #2 ........ 134 4.5.3.14 ROMADR - Video BIOS ROM Base Address Registers Device #2 ...... 135 4.5.3.15 CAPPOINT - Capabilities Pointer Register - Device #2 ...... 135 4.5.3.16 INTRLINE - Interrupt Line Register - Device #2... 135 4.5.3.17 INTRPIN - Interrupt Pin Register - Device #2 ...... 136 4.5.3.18 MINGNT - Minimum Grant Register - Device #2.. 136 4.5.3.19 MAXLAT - Maximum Latency Register - Device #2............ 136 4.5.3.20 PMCAPID - Power Management Capabilities ID Register - Device #2 ...... 137
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