|
Details, datasheet, quote on part number:840
| |
| Part: | 840 |
| Category: | Interface and Interconnect => Chipsets |
| Description: | 840 Chipset: 82840 Memory Controller Hub (MCH) |
| Company: | Intel Corporation |
| Datasheet: | Download 840 datasheet File size : 888 kB |
| Request For quote: | Find where to buy 840
|
| |
Datasheet text preview:
R
Intel® 840 Chipset: 82840 Memory Controller Hub (MCH)
Datasheet
September 2000
Document Number: 298020-002
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® 82840 MCH may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation www.intel.com or call 1-800-548-4725 *Third-party brands and names are the property of their respective owners. Copyright © Intel Corporation 2000
2
Datasheet
82840 MCH
R
Contents
1. Overview....13 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. Intel 840 Chipset System Architecture ....... 13 82840 MCH Overview .......... 16 Terminology .......... 18 Host Interface Signals ..........22 Direct Rambus* Interface A .......... 24 Direct Rambus* Interface B .......... 25 Hub Interface A Signals ....... 26 Hub interface B Signals........26 AGP Interface Signals..........26 2.6.1. AGP Addressing Signals .. 26 2.6.2. AGP Flow Control Signals ......... 27 2.6.3. AGP Status Signals .......... 28 2.6.4. AGP Clocking Signals--Strobes ..... 28 2.6.5. AGP FRAME# Signals......29 Clocks, Reset, and Miscellaneous ......... 31 Voltage References, PLL Power ... 32 Strap Signals.........33 Register Nomenclature and Access Attributes ..... 35 PCI Configuration Space Access .. 36 I/O Mapped Registers .......... 39 3.3.1. CONF_ADDRConfiguration Address Register .... 39 3.3.2. CONF_DATA--Configuration Data Register.....40 Host-Hub interface A Bridge/DRAM Controller Device Registers (Device 0) ....... 41 3.4.1. VID--Vendor Identification Register (Device 0) ...... 44 3.4.2. DID--Device Identification Register (Device 0).......44 3.4.3. PCICMD--PCI Command Register (Device 0) ....... 45 3.4.4. PCISTS--PCI Status Register (Device 0).........46 3.4.5. RID--Revision Identification Register (Device 0)....47 3.4.6. SUBC--Sub-Class Code Register (Device 0).........47 3.4.7. BCC--Base Class Code Register (Device 0)....47 3.4.8. MLT--Master Latency Timer Register (Device 0) ............ 48 3.4.9. HDR--Header Type Register (Device 0) .......... 48 3.4.10. --Aperture Base Configuration Register (Device 0).........48 3.4.11. SVID--Subsystem Vendor ID (Device 0) .......... 50 3.4.12. SID--Subsystem ID (Device 0) ....... 50 3.4.13. CAPPTR--Capabilities Pointer (Device 0) ........ 50 3.4.14. GAR[15:0]--RDRAM Group Architecture Register (Device 0)..51 3.4.15. MCHCFG--MCH Configuration Register (Device 0)........52 3.4.16. FDHC--Fixed DRAM Hole Control Register (Device 0)...53 3.4.17. PAM0PAM6--Programmable Attribute Map Registers (Device 0) ....... 54 3.4.18. GBA0GBA15--RDRAM Group Boundary Address Register (Device 0) ........ 57 3.4.19. RDPS--RDRAM Pool Sizing Register (Device 0) ............ 58
®
Signal Description.....21
2.7. 2.8. 2.9. 3. 3.1. 3.2. 3.3.
Register Description .......... 35
3.4.
Datasheet
3
3.4.20. 3.4.21. 3.4.22. 3.4.23. 3.4.24.
3.5.
DRD--RDRAM Device Register Data Register (Device 0) ...... 59 RICM--RDRAM Initialization Control Management Register (Device 0).......... 59 MCH Expansion RAC A/B Configuration Registers ......... 61 SMRAM--System Management RAM Control Register (Device 0) ....... 61 ESMRAMC--Extended System Management RAM Control Register (Device 0) .......... 62 3.4.25. ACAPID--AGP Capability Identifier Register (Device 0) .......... 63 3.4.26. AGPSTAT--AGP Status Register (Device 0)......... 64 3.4.27. AGPCMD--AGP Command Register (Device 0) ............ 65 3.4.28. AGPCTRL--AGP Control Register (Device 0) ....... 66 3.4.29. APSIZE--Aperture Size (Device 0) ......... 66 3.4.30. ATTBASE Aperture Translation Table Base Register (Device 0) ....... 67 3.4.31. AMTT--AGP Interface Multi-Transaction Timer Register (Device 0) ..... 67 3.4.32. LPTT--Low Priority Transaction Timer Register (Device 0)..... 68 3.4.33. RDTR--RDRAM Timing Register (Device 0) ......... 69 3.4.34. RDCR--RDRAM Refresh Control Register (Device 0).... 70 3.4.35. TOM--Top of Low Memory Register (Device 0)..... 71 3.4.36. ERRSTS--Error Status Register (Device 0)..... 71 3.4.37. ERRCMD--Error Command Register (Device 0) ............ 73 3.4.38. SMICMD--SMI Command Register (Device 0)...... 75 3.4.39. SCICMD--SCI Command Register (Device 0)....... 77 3.4.40. SKPD--Scratchpad Data (Device 0) ....... 78 3.4.41. HERRCTL_STS--Host Error Control/Status Register (Device 0) ........... 79 3.4.42. DERRCTL_STS--DRAM Error Control/Status Register (Device 0) ....... 80 3.4.43. EAP--Error Address Pointer Register (Device 0)............ 80 3.4.44. AGPBCTRL--AGP Buffer Strength Control Register ...... 81 3.4.45. AGPAPPEND--AGP Append Disable Register...... 81 3.4.46. GTLNCLAMP--GTL N Clamp Disable Register..... 81 AGP Bridge Registers (Device 1) .......... 82 3.5.1. VID1--Vendor Identification Register (Device 1).... 83 3.5.2. DID1--Device Identification Register (Device 1) .... 83 3.5.3. PCICMD1--PCI-PCI Command Register (Device 1) ...... 84 3.5.4. PCISTS1--PCI-PCI Status Register (Device 1) ..... 85 3.5.5. RID1--Revision Identification Register (Device 1) .......... 85 3.5.6. SUBC1--Sub-Class Code Register (Device 1) ...... 86 3.5.7. BCC1--Base Class Code Register (Device 1) ....... 86 3.5.8. MLT1--Master Latency Timer Register (Device 1) ......... 86 3.5.9. HDR1--Header Type Register (Device 1) ........ 86 3.5.10. PBUSN1--Primary Bus Number Register (Device 1)...... 87 3.5.11. SBUSN1--Secondary Bus Number Register (Device 1) .......... 87 3.5.12. SUBUSN1--Subordinate Bus Number Register (Device 1) ..... 87 3.5.13. SMLT1--Secondary Master Latency Timer Register (Device 1) .... 88 3.5.14. IOBASE1--I/O Base Address Register (Device 1) .......... 88 3.5.15. IOLIMIT1--I/O Limit Address Register (Device 1)........... 89 3.5.16. SSTS1--Secondary PCI-PCI Status Register (Device 1)......... 89 3.5.17. MBASE1--Memory Base Address Register (Device 1)... 90 3.5.18. MLIMIT1--Memory Limit Address Register (Device 1) ... 91 3.5.19. PMBASE1--Prefetchable Memory Base Address Register (Device 1) ... 91 3.5.20. PMLIMIT1--Prefetchable Memory Limit Address Register (Device 1).... 92 3.5.21. BCTRL1--PCI-PCI Bridge Control Register (Device 1) .. 92 3.5.22. ERRCMD1--Error Command Register (Device 1) .......... 94
4
Datasheet
82840 MCH
R
3.6.
Hub interface B Bridge Registers (Device 2) ........ 95 3.6.1. VID2--Vendor Identification Register (Device 2) .... 96 3.6.2. DID2--Device Identification Register (Device 2).....96 3.6.3. PCICMD2--PCI-PCI Command Register (Device 2).......97 3.6.4. PCISTS2--PCI-PCI Status Register (Device 2)......98 3.6.5. RID2--Revision Identification Register (Device 2)...........98 3.6.6. SUBC2--Sub-Class Code Register (Device 2).......99 3.6.7. BCC2--Base Class Code Register (Device 2)........99 3.6.8. MLT2--Master Latency Timer Register (Device 2) .......... 99 3.6.9. HDR2--Header Type Register (Device 2) ........ 99 3.6.10. PBUSN2--Primary Bus Number Register (Device 2) .... 100 3.6.11. SBUSN2--Secondary Bus Number Register (Device 2) ........ 100 3.6.12. SUBUSN2--Subordinate Bus Number Register (Device 2)....100 3.6.13. SMLT2--Secondary Master Latency Timer Register (Device 2) ........... 100 3.6.14. IOBASE2--I/O Base Address Register (Device 2) ........ 101 3.6.15. IOLIMIT2--I/O Limit Address Register (Device 2) ......... 101 3.6.16. SSTS2--Secondary PCI-PCI Status Register (Device 2) ....... 102 3.6.17. MBASE2--Memory Base Address Register (Device 2) .......... 103 3.6.18. MLIMIT2--Memory Limit Address Register (Device 2) .. 103 3.6.19. PMBASE2--Prefetchable Memory Base Address Register (Device 2) .......... 104 3.6.20. PMLIMIT2--Prefetchable Memory Limit Address Register (Device 2) .. 104 3.6.21. BCTRL2--PCI-PCI Bridge Control Register (Device 2) .......... 105 3.6.22. ERRCMD2--Error Command Register (Device 2) ........ 106 Memory Address Ranges............107 4.1.1. DOS Compatibility Area..108 4.1.2. Extended Memory Area..110 4.1.3. AGP Memory Address Ranges ..... 112 4.1.4. AGP DRAM Graphics Aperture ..... 113 4.1.5. System Management Mode (SMM) Memory Range ...... 113 4.1.5.1. SMM Space Definition.....114 4.1.5.2. SMM Space Restrictions .......... 114 4.1.6. Memory Shadowing........115 4.1.7. I/O Address Space ......... 115 4.1.7.1. AGP I/O Address Mapping ....... 115 4.1.8. MCH Decode Rules and Cross-Bridge Address Mapping.......116 4.1.8.1. The Hub interface A Decode Rules.........116 4.1.8.2. The Hub interface B Decode Rules.........116 4.1.8.3. AGP Interface Decode Rules ... 117 4.1.8.4. Legacy VGA Ranges.......118
4.
System Address Map.......107 4.1.
Datasheet
5
|
|
