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Details, datasheet, quote on part number:855GM
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Intel® 855GM Chipset Graphics and Memory Controller Hub (GMCH)
Datasheet
March 2003
Order Number: 252615-001
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power characteristics, system power and thermal management techniques, software application usage and general system design. Intel is not responsible for its customers' system designs, nor is Intel responsible for ensuring that its customers' products comply with all applicable laws and regulations. Intel provides this and other thermal design information for informational purposes only. System design is the sole responsibility of Intel's customers, and Intel's customers should not rely on any Intel-provided information as either an endorsement or recommendation of any particular system design characteristics. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® 855GM Chipset Graphics and Memory Controller Hub (GMCH) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a 2-wire communications bus/protocol developed by Philips*. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Alert on LAN* is a result of the Intel and IBM* Advanced Manageability Alliance and a trademark of IBM. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation www.intel.com or call 1-800-548-4725 Intel, the Intel logo, Pentium, and Intel SpeedStep, Intel Centrino are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and other countries. *Other brands and names may be claimed as the property of others. Copyright © Intel Corporation 2003
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Intel® 855GM Chipset GMCH Datasheet
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Contents
1. Introduction ...... 17 1.1. Terminology .......... 17 1.2. Reference Documents ......... 19 1.3. System Architecture.............20 1.4. Processor Host Interface ..... 21 1.5. Intel 855GM GMCH Host Bus Error Checking......21 1.6. Intel 855GM GMCH System Memory Interface .... 21 1.7. Intel 855GM GMCH Internal Graphics.........22 1.7.1. Intel 855GM GMCH Analog Display Port ......... 23 1.7.2. Intel 855GM GMCH Integrated LVDS Port.......23 1.7.3. Intel 855GM GMCH Integrated DVO Ports ...... 23 1.8. Hub Interface ........ 23 1.9. Address Decode Policies ..... 23 1.10. Intel 855GM GMCH Clocking ....... 24 1.11. System Interrupts..25 Signal Description.....27 2.1. Host Interface Signals..........28 2.2. DDR SDRAM Interface ........ 30 2.3. Hub Interface Signals...........31 2.4. Clocks .......... 32 2.5. Internal Graphics Display Signals..........34 2.5.1. Dedicated LVDS LCD Flat Panel Interface ...... 34 2.5.2. Digital Video Output B (DVOB) Port........35 2.5.3. Digital Video Output C (DVOC) Port ....... 36 2.5.4. Analog CRT Display ........ 37 2.5.5. General Purpose Input/Output Signals....38 2.6. Voltage References, PLL Power...40 Register Description .......... 42 3.1. Conceptual Overview of the Platform Configuration Structure ..... 43 3.2. Nomenclature for Access Attributes ...... 44 3.3. Standard PCI Bus Configuration Mechanism ....... 45 3.4. Routing Configuration Accesses...45 3.4.1. PCI Bus #0 Configuration Mechanism .... 45 3.4.2. Primary PCI and Downstream Configuration Mechanism........45 3.5. Register Definitions........46 3.6. I/O Mapped Registers .......... 47 3.6.1. CONFIG_ADDRESS Configuration Address Register..........47 3.6.2. CONFIG_DATA Configuration Data Register ..... 49 3.7. VGA I/O Mapped Registers .......... 50 3.8. Intel 855GM GMCH Host-Hub Interface Bridge Device Registers (Device #0, Function #0)..........51 3.8.1. VID Vendor Identification Register ....... 52 3.8.2. DID Device Identification Register........52 3.8.3. PCICMD PCI Command Register ........ 53 3.8.4. PCI Status Register ......... 54 3.8.5. RID Register Identification...........55
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Intel® 855GM Chipset GMCH Datasheet
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3.9.
3.10.
3.11.
3.8.6. SUBC Sub Class Code Register .......... 55 3.8.7. BCC Base Class Code Register...........56 3.8.8. HDR Header Type Register.........56 3.8.9. SVID Subsystem Vendor Identification Register .......... 56 3.8.10. SID Subsystem Identification Register .......... 57 3.8.11. CAPPTR Capabilities Pointer Register ......... 57 3.8.12. CAPIDCapability Identification Register (Device #0) ... 58 3.8.13. GMC GMCH Miscellaneous Control Register (Device #0)....59 3.8.14. GGC GMCH Graphics Control Register (Device 0) ..... 60 3.8.15. DAFC Device and Function Control Register (Device 0) ...... 61 3.8.16. FDHC Fixed DRAM Hole Control Register (Device #0) ........ 61 3.8.17. PAM(6:0) Programmable Attribute Map Register (Device #0) .... 62 3.8.18. SMRAM System Management RAM Control Register (Device #0) ..... 66 3.8.19. ESMRAMC Extended System Management RAM Control (Device #0) ....... 67 3.8.20. ERRSTS Error Status Register (Device #0)........68 3.8.21. ERRCMD Error Command Register (Device #0) ......... 69 3.8.22. SMICMD SMI Error Command Register (Device #0) ... 71 3.8.23. SCICMD SCI Error Command Register (Device 0)......72 Intel 855GM GMCH Main Memory Control, Memory I/O Control Registers (Device #0, Function #1)..........73 3.9.1. VID Vendor Identification Register ....... 74 3.9.2. DID Device Identification Register........74 3.9.3. PCICMD PCI Command Register ........ 75 3.9.4. PCISTS PCI Status Register ....... 76 3.9.5. RID Revision Identification Register.....77 3.9.6. SUBC Sub-Class Code Register..........77 3.9.7. BCC Base Class Code Register...........77 3.9.8. HDR Header Type Register.........78 3.9.9. SVID Subsystem Vendor Identification Register .......... 78 3.9.10. SID Subsystem Identification Register .......... 78 3.9.11. CAPPTR Capabilities Pointer Register ......... 79 3.9.12. DRB DRAM Row (0:3) Boundary Register (Device #0) ........ 79 3.9.13. DRA DRAM Row Attribute Register (Device #0)..........80 3.9.14. DRT DRAM Timing Register (Device #0)......81 3.9.15. PWRMG DRAM Controller Power Management Control Register (Device #0) ............. 84 3.9.16. DRC DRAM Controller Mode Register (Device #0)......86 3.9.17. DTC DRAM Throttling Control Register (Device #0) .... 89 Intel 855GM GMCH Configuration Process Registers (Device #0, Function #3) .......... 93 3.10.1. VID Vendor Identification Register ....... 93 3.10.2. DID Device Identification Register........94 3.10.3. PCICMD PCI Command Register ........ 95 3.10.4. PCISTS PCI Status Register ....... 96 3.10.5. RID Revision Identification Register.....97 3.10.6. SUBC Sub-Class Code Register..........97 3.10.7. BCC Base Class Code Register...........97 3.10.8. HDR Header Type Register.........98 3.10.9. SVID Subsystem Vendor Identification Register .......... 98 3.10.10. ID Subsystem Identification Register ... 98 3.10.11. CAPPTR Capabilities Pointer Register ......... 99 3.10.12. HPLLCC HPLL Clock Control Register (Device #0).....99 Intel 852GM GMCH Integrated Graphics Device Registers (Device #2, Function #0) ........101
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Intel® 855GM Chipset GMCH Datasheet
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3.11.1. VID Vendor Identification Register (Device #2)..........102 3.11.2. DID Device Identification Register (Device #2) ..........102 3.11.3. PCICMD PCI Command Register (Device #2)...........103 3.11.4. PCISTS PCI Status Register (Device #2) .........104 3.11.5. RID Revision Identification Register (Device #2) .......104 3.11.6. CC Class Code Register (Device #2)..........105 3.11.7. CLS Cache Line Size Register (Device #2) ......105 3.11.8. MLT Master Latency Timer Register (Device #2).......105 3.11.9. HDR Header Type Register (Device #2) .....106 3.11.10. GMADR Graphics Memory Range Address Register (Device #2).....106 3.11.11. MMADR Memory Mapped Range Address Register (Device #2) ......107 3.11.12. IOBAR I/O Base Address Register (Device #2) .........107 3.11.13. SVID Subsystem Vendor Identification Register (Device #2) ............108 3.11.14. SID Subsystem Identification Register (Device #2) ...108 3.11.15. ROMADR Video BIOS ROM Base Address Registers (Device #2) ...108 3.11.16. INTRLINEInterrupt Line Register (Device #2) ...........109 3.11.17. INTRPINInterrupt Pin Register (Device #2) ......109 3.11.18. MINGNT Minimum Grant Register (Device #2)..........109 3.11.19. MAXLAT Maximum Latency Register (Device #2) ....109 3.11.20. PMCAP Power Management Capabilities Register (Device #2)........110 3.11.21. PMCS Power Management Control/Status Register (Device #2) ......110 4. Intel 855GM GMCH System Address Map.......111 4.1. System Memory Address Ranges .......111 4.2. DOS Compatibility Area .....113 4.3. Extended System Memory Area ..........115 4.4. Main System Memory Address Range (0010_0000h to Top of Main Memory) ..........116 4.4.1. 15 MB-16 MB Window...116 4.4.2. Pre-allocated System Memory .....116 4.4.2.1. Extended SMRAM Address Range (HSEG and TSEG) ......117 4.4.2.2. HSEG ...........117 4.4.2.3. TSEG............117 4.4.2.4. Dynamic Video Memory Technology (DVMT).......117 4.4.2.5. PCI Memory Address Range (Top of Main System Memory to 4 GB) ......117 4.4.2.6. APIC Configuration Space (FEC0_0000h -FECF_FFFFh, FEE0_0000h- FEEF_FFFFh)........118 4.4.2.7. High BIOS Area (FFE0_0000h -FFFF_FFFFh) ....118 4.4.3. System Management Mode (SMM) Memory Range .....118 4.4.3.1. SMM Space Restrictions......119 4.4.3.2. SMM Space Definition..........119 4.4.4. System Memory Shadowing.........119 4.4.5. I/O Address Space ........119 4.4.6. GMCH Decode Rules and Cross-Bridge Address Mapping...120 4.4.7. Hub Interface Decode Rules ........120 4.4.7.1. Hub Interface Accesses to GMCH that Cross Device Boundaries ...121 Functional Description .....123 5.1. Host Interface Overview.....123 5.2. Dynamic Bus Inversion ......123 5.2.1. System Bus Interrupt Delivery ......123 5.2.2. Upstream Interrupt Messages ......124
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Intel® 855GM Chipset GMCH Datasheet
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