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Details, datasheet, quote on part number:855PM
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| Part: | 855PM |
| Category: | Interface and Interconnect => Chipsets |
| Description: | Intel 855PM Chipset Memory Controller Hub (MCH) |
| Company: | Intel Corporation |
| Datasheet: | Download 855PM datasheet File size : 1629 kB |
| Request For quote: | Find where to buy 855PM
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Datasheet text preview:
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Intel® 855PM Chipset Memory Controller Hub (MCH) DDR 200/266 MHz
Datasheet
March 2003
Order Number: 252613-001
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® 855PM Memory Controller Hub (MCH) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a 2-wire communications bus/protocol developed by Philips*. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Wireless connectivity and some features may require you to purchase additional software, services or external hardware. Availability of public wireless LAN access points limited. System performance measured by MobileMark* 2002. System performance, battery life, wireless performance and functionality will vary depending on your specific hardware and software configurations. See http://www.intel.com/products/centrino/more_info for more information. Alert on LAN* is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM*. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation www.intel.com or call 1-800-548-4725 Intel, the Intel logo, and Intel Enhanced SpeedStep are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and other countries. Intel, Intel Logo, Pentium, and Intel Centrino are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other brands and names may be claimed as the property of others. Copyright © Intel Corporation 2003
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Intel® 855PM Chipset Memory Controller Hub (MCH) DDR 200/266 MHz Datasheet
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Contents
1. Introduction ...... 15 1.1. Reference Documents ......... 16 1.2. Terminology .......... 17 1.3. System Architecture.............18 1.4. Processor Host Interface ..... 18 1.4.1. Host Bus Error Checking .......... 19 1.5. DRAM Interface .... 19 1.6. AGP Interface ....... 21 1.7. Hub Interface ........ 21 1.8. MCH Clocking ....... 21 1.9. System Interrupts..22 Signal Description.....23 2.1. Host Interface Signals..........24 2.2. DDR Interface ....... 26 2.3. Hub Interface Signals...........27 2.4. AGP Interface Signals..........27 2.4.1. AGP Addressing Signals .......... 27 2.4.2. AGP Flow Control Signals ........ 28 2.4.3. AGP Status Signals ......... 28 2.4.4. AGP Strobes ...........29 2.4.5. AGP/PCI Signals-Semantics .......... 30 2.5. Clocks, Reset, and Miscellaneous.........32 2.6. Voltage References, PLL Power...33 2.7. Reset States and Pull-up/Pull-downs .......... 34 Register Description .......... 39 3.1. Conceptual Overview of the Platform Configuration Structure ..... 39 3.2. Standard PCI Bus Configuration Mechanism ....... 39 3.3. Routing Configuration Accesses...40 3.3.1. PCI Bus #0 Configuration Mechanism.....40 3.3.2. Primary PCI and Downstream Configuration Mechanism ........ 40 3.3.3. AGP Configuration Mechanism ...... 41 3.4. MCH Register Introduction ........... 41 3.5. I/O Mapped Registers .......... 42 3.5.1. CONFIG_ADDRESS Configuration Address Register .......... 42 3.5.2. CONFIG_DATA - Configuration Data Register ...... 44 3.6. Memory Mapped Register Space .......... 44 3.6.1. SMRCTL System Memory RCOMP Control Register Device #0 ....... 45 3.6.2. DRAMWIDTH DRAM Width Register ... 46 3.6.3. DCLKDIS DRAM Clock Control Disable Register ........ 46 3.6.4. DQCMDSTR Strength Control Register for DQ and CMD Signal Groups .... 49 3.6.5. CKESTR Strength Control Register for CKE Signal Group...50 3.6.6. CSBSTR Strength Control Register for CS# Signal Group ... 51 3.6.7. CKSTR Strength Control Register for CK Signal Group (CK / CK#) .... 52 3.6.8. RCVENSTR Strength Control Register for RCVENOUT# Signals.......53 3.6.9. CGREDSTR Strength Control Register for CMD Group Reduced Strength Signals ..... 54 3.7. Host-Hub Interface Bridge Device Registers Device #0............54
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Intel® 855PM Chipset Memory Controller Hub (MCH) DDR 200/266 MHz Datasheet
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3.8.
3.7.1. VID Vendor Identification Register Device#0 ............ 57 3.7.2. DID Device Identification Register Device#0 ............ 57 3.7.3. PCICMD PCI Command Register Device #0 ............ 58 3.7.4. PCISTS PCI Status Register Device #0..... 59 3.7.5. RID Revision Identification Register Device #0 ........ 60 3.7.6. SUBC Sub-Class Code Register Device #0..... 60 3.7.7. BCC Base Class Code Register Device #0 ..... 60 3.7.8. MLT Master Latency Timer Register Device #0........ 61 3.7.9. HDR Header Type Register Device #0 ...... 61 3.7.10. APBASE Aperture Base Configuration Register Device #0..... 62 3.7.11. SMRBASE System Memory RCOMP Base Address Register Device #0 . 63 3.7.12. SVID Subsystem Vendor ID Device #0...... 63 3.7.13. SID Subsystem ID Device #0............ 64 3.7.14. CAPPTR Capabilities Pointer Device #0.... 64 3.7.15. AGPM AGP Miscellaneous Configuration Device #0......... 64 3.7.16. DQSMRG DQS Margining Control Register Device #0 ..... 65 3.7.17. DRB DRAM Row Boundary Register Device #0 ....... 65 3.7.18. DRA DRAM Row Attribute Register Device #0 ......... 66 3.7.19. DRT DRAM Timing Register Device #0 ..... 67 3.7.20. DRC DRAM Controller Mode Register Device #0..... 71 3.7.21. DRDCTL DRAM Read Timing Control Register Device #0 ..... 73 3.7.22. DORC DRAM Opportunistic Refresh Control Register Device #0 .... 74 3.7.23. DQSCTL DQS Control Register Device #0...... 74 3.7.24. ECCDIAG - ECC Diagnostic Control Register Device #0 ..... 75 3.7.25. DERRSYN DRAM Error Syndrome Register Device #0 .... 75 3.7.26. DES DRAM Error Status Register Device #0............ 76 3.7.27. DEAP DRAM Error Address Pointer Register Device #0... 77 3.7.28. PAM[0:6] Programmable Attribute Map Registers Device #0 ........... 78 3.7.29. FDHC Fixed DRAM Hole Control Register Device #0 ....... 82 3.7.30. SMRAM System Management RAM Control Register Device #0 .... 83 3.7.31. ESMRAMC Extended System Mgmt RAM Control Register Device #0 .... 84 3.7.32. ACAPID AGP Capability Identifier Register Device #0 ...... 85 3.7.33. AGPSTAT AGP Status Register Device #0 ..... 86 3.7.34. AGPCMD AGP Command Register Device #0......... 87 3.7.35. AGPCTRL AGP Control Register......... 88 3.7.36. APSIZE Aperture Size Device #0...... 89 3.7.37. ATTBASE Aperture Translation Table Base Register Device #0 ..... 90 3.7.38. AMTT AGP Interface Multi-Transaction Timer Register Device #0 .. 91 3.7.39. LPTT AGP Low Priority Transaction Timer Register Device #0 ....... 92 3.7.40. TOM Top of Low Memory Register Device #0 .......... 92 3.7.41. MCHCFG MCH Configuration Register Device #0 ... 93 3.7.42. ERRSTS Error Status Register Device #0 ....... 94 3.7.43. ERRCMD Error Command Register Device #0 ........ 96 3.7.44. SMICMD SMI Command Register Device #0 ........... 98 3.7.45. SCICMD SCI Command Register Device #0 ............ 99 3.7.46. WCCTL Write Cache Control Register Device #0 .. 100 3.7.47. SKPD Scratchpad Data Device #0.. 101 3.7.48. CAPID Product Specific Capability register Device #0 .... 101 3.7.49. MCHTST MCH Test Register Device #0........ 102 AGP Bridge Registers Device #1 ........... 102 3.8.1. VID1 Vendor Identification Register Device #1 ....... 105 3.8.2. DID1 Device Identification Register Device #1 ....... 105 3.8.3. PCICMD1 PCI-PCI Command Register Device #1.......... 106 3.8.4. PCISTS1 PCI-PCI Status Register Device #1 ........ 107
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Intel® 855PM Chipset Memory Controller Hub (MCH) DDR 200/266 MHz Datasheet
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3.9.
RID1 Revision Identification Register Device #1 .....108 SUBC1- Sub-Class Code Register Device #1............108 BCC1 Base Class Code Register Device #1...........109 MLT1 Master Latency Timer Register Device #1 ....109 HDR1 Header Type Register Device #1.........109 PBUSN1 Primary Bus Number Register Device #1 .........110 SBUSN1 Secondary Bus Number Register Device #1 ....110 SUBUSN1 Subordinate Bus Number Register Device #1......110 SMLT1 Secondary Master Latency Timer Register Device #1 .......111 IOBASE1 I/O Base Address Register Device #1.....112 IOLIMIT1 I/O Limit Address Register Device #1......112 SSTS1 Secondary PCI-PCI Status Register Device #1 ...113 MBASE1 Memory Base Address Register Device #1 ......114 MLIMIT1 Memory Limit Address Register Device #1 .......115 PMBASE1 Prefetchable Memory Base Address Register Device #1 ......116 PMLIMIT1 Prefetchable Memory Limit Address Register Device #1 .......117 BCTRL1 PCI-PCI Bridge Control Register Device #1 ......118 ERRCMD1 Error Command Register Device #1.....119 DWTC DRAM Write Throttling Control Register Device #1....120 DRTC DRAM Read Throttling Control Register Device #1 ....122 TSCR Thermal Sensor Control Register Device #1 .........124 TSSR Thermal Sensor Status Register Device #1..125 THTS Thermal Sensor High Temperature Setting Register Device #1....125 TCTS Thermal Sensor Catastrophic Temperature Setting Register Device #1 ..........126 3.8.29. TCOR Thermal Calibration Offset Register Device #1 .....126 3.8.30. TSHTC Thermal Sensor Hardware Throttling Control Register Device #1 ..........127 Power Management Registers Device #6 .......128 3.9.1. VID6 Vendor Identification Register Device #6 .......129 3.9.2. DID6 Device Identification Register Device #6........130 3.9.3. PCICMD6 PCI Command Register Device #6 ........130 3.9.4. PCISTS6 PCI Status Register Device #6 .......131 3.9.5. RID6 Revision Identification Register Device #6 .....131 3.9.6. SUBC6- Sub-Class Code Register Device #6............132 3.9.7. BCC6 Base Class Code Register Device #6...........132 3.9.8. HDR6 Header Type Register Device #6.........132 3.9.9. BAR6 Base Address Register Device #6 .......133 3.9.10. PMCR Power Management Control Register Device #6..134 3.9.11. PMCER Power Management Control Extension Register Device #6 ......135
3.8.5. 3.8.6. 3.8.7. 3.8.8. 3.8.9. 3.8.10. 3.8.11. 3.8.12. 3.8.13. 3.8.14. 3.8.15. 3.8.16. 3.8.17. 3.8.18. 3.8.19. 3.8.20. 3.8.21. 3.8.22. 3.8.23. 3.8.24. 3.8.25. 3.8.26. 3.8.27. 3.8.28.
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System Address Map ......137 4.1. Memory Address Ranges ...........137 4.1.1. VGA and MDA Memory Space .....138 4.1.2. PAM Memory Spaces ....139 4.1.3. ISA Hole Memory Space ........140 4.1.4. TSEG SMM Memory Space .........140 4.1.5. IOAPIC Memory Space ..........141 4.1.6. System Bus Interrupt Memory Space ....141 4.1.7. High SMM Memory Space......141 4.1.8. AGP Aperture Space (Device #0 BAR) ..........141 4.1.9. AGP Memory and Prefetchable Memory........142 4.1.10. Hub Interface A Subtractive Decode .....142 4.2. AGP Memory Address Ranges...142
Intel® 855PM Chipset Memory Controller Hub (MCH) DDR 200/266 MHz Datasheet
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