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Details, datasheet, quote on part number:8742
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| Part: | 8742 |
| Category: | Interface and Interconnect => Controllers |
| Description: | Universal Peripheral Interface 8-bit Slave Microcontroller |
| Company: | Intel Corporation |
| Datasheet: | Download 8742 datasheet File size : 216 kB |
| Request For quote: | Find where to buy 8742
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Datasheet text preview:
8742 UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER
Y Y
8742 12 MHz Pin Software and Architecturally Compatible with 8741A 8-Bit CPU plus ROM RAM I O Timer and Clock in a Single Package 2048 x 8 EPROM 128 x 8 RAM 8-Bit Timer Counter 18 Programmable I O Pins One 8-Bit Status and Two Data Registers for Asynchronous Slave-toMaster Interface
Y
DMA Interrupt or Polled Operation Supported Fully Compatible with all Intel and Most Other Microprocessor Families Expandable I O RAM Power-Down Capability Over 90 Instructions 70% Single Byte Available in EXPRESS Standard Temperature Range
Y
Y
Y Y Y Y
Y
Y
The Intel 8742 is a general-purpose Universal Peripheral Interface that allows designers to grow their own customized solution for peripheral device control It contains a low-cost microcomputer with 2K of program I memory 128 bytes of data memory 8-bit timer counter and clock generator in a single 40-pin package nterface registers are included to enable the UPI device to function as a peripheral controller in the MCS -48 T MCS-51 MCS-80 MCS-85 8088 8086 and other 8- 16-bit systems he 8742 is software pin and architecturally compatible with the 8741A The 8742 doubles the on-chip memory space to allow for additional features and performance to be incorporated in upgraded 8741A designs For new designs the additional memory and performance of the 8742 extends the UPI concept to more complex motor control tasks 80-column printers and process control app2ications as examples l
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Figure 1 Pin Configuration
November 1991
Order Number 290256-001
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8742
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Figure 2 Block Diagram
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2
8742
Table 1 Pin Description
Symbol T EST 0 TEST 1 DIP Pin No 1 39 Type Name and Function
I
X TAL 1 XTAL 2 RESET S S C S E A R D A
0
TEST INPUTS Input pins which can be directly tested using conditional branch instructions FREQUENCY REFERENCE TEST 1 (T1) also functions as the event timer input (under software control) TEST 0 (T0) is used during PROM programming and EPROM verification INPUTS Inputs for a crystal LC or an external timing signal to determine the internal oscillator frequency RESET Input used to reset status flip-flops and to set the program counter to zero ESET is also used during EPROM programming and verification SINGLE STEP Single step input used in conjunction with the SYNC output to step the program through each instruction (EPROM) This should be tied to a 5V when not used CHIP SELECT Chip select input used to select one UPI microcomputer out of several connected to a common data bus EXTERNAL ACCESS External access input which allows emulation testing and EPROM verification This pin should be tied low if unused READ I O read input which enables the master CPU to read data and status words from the OUTPUT DATA BUS BUFFER or status register COMMAND DATA SELECT Address Input used by the master processor to indicate whether byte transfer is data (A0 e 0 F1 is reset) or command (A0 e 1 F1 is set) A0 e 0 during program and verify operations WRITE I O write input which enables the master CPU to write data and command words to the UPI INPUT DATA BUS BUFFER OUTPUT CLOCK Output signal which occurs once per UPI instruction cycle SYNC can be used as a strobe for external circuitry it is also used to synchronize single step operation DATA BUS Three-state bidirectional DATA BUS BUFFER lines used to interface the UPI microcomputer to an 8-bit master system data bus PORT 1 8-bit PORT 1 quasi-bidirectional I O lines PORT 2 8-bit PORT 2 quasi-bidirectional I O lines The lower 4 bits (P20 P23) interface directly to the 8243 I O expander device and contain address and data information during PORT 4 7 access The upper 4 bits (P24 P27) can be programmed to provide interrupt Request and DMA Handshake capability Software control can configure P24 as Output Buffer Full (OBF) interrupt P25 as Input Buffer Full (IBF) interrupt P26 as DMA Request (DRQ) and P27 as DMA ACKnowledge (DACK) D PROGRAM Multifunction pin used as the program pulse input during PROM programming T uring I O expander access the PROG pin acts as an address data strobe to the 8243 his pin should be tied high if unused POWER a5V main power supply pin POWER a5V during normal operation a21V during programming operation Low power standby supply pin GROUND Circuit ground potential 3
2 3 4 5 6 7 8 9
I I I I I I I
W R S YNC ( D0 D7 P US) B P10 P17
20 P27
10 11
I O
12 19 27 34 21 24 35 38
IO IO IO
P ROG V VCC
DD
25
IO
40 26 20
V
SS
3
8742
the IBF Status Bit A ``0'' written to P25 disables the IBF pin (the pin remains low) This pin can be used to indicate that the UPI is ready 2 or data f
UPI-42 FEATURES
1 Two Data Bus Buffers one for input and one for output This allows a much cleaner Master Slave protocol 2
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Data Bus Buffer Interrupt Capability
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2 8 Bits of Status ST7 ST6 ST5 ST4 F1 F0 IBF OBF D7 D6 D5 D4 D3 D2 D1 D0 ST4 ST7 are user definable status bits These s bits are defined by the ``MOV STS A'' single byte ingle cycle instruction Bits 4 7 of the acccumuB lator are moved to bits 4 7 of the status register itM 0 3 of the status register are not affected s
OV STS A Op Code 90H
1
1
1
1
0
1
0
1
1
0
0
1
0
0
0
0
D7 D0 3 RD and WR are edge triggered IBF OBF F1 and INT change internally after the trailing edge of RD or WR 2
D7 D0 5 P26 and P27 are port pins or DMA handshake pins for use with a DMA controller These pins default I to port pins on Reset P the ``EN DMA'' instruction has been executed f 26 becomes the DRQ (DMA Request) pin A ``1'' written to P26 causes a DMA request (DRQ is actiD ted) DRQ is deactivated by DACK # RD va ACK # WR or execution of the ``EN DMA'' inI struction f ``EN DMA'' has been executed P27 becomes the DACK (DMA Acknowledge) pin This pin acts as a chip select input for the Data Bus Buffer registers during DMA transfers 2
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During the time that the host CPU is reading the status register the 8742 is prevented from updat4 ing this register or is ``locked out'' P24 and P25 are port pins or Buffer Flag pins which can be used to interrupt a master procesI sor These pins default to port pins on Reset f the ``EN FLAGS'' instruction has been executed P24 becomes the OBF (Output Buffer Full) pin A ``1'' written to P24 enables the OBF pin (the pin outputs the OBF Status Bit) A ``0'' written to P24 disables the OBF pin (the pin remains low) This pin can be used to indicate that valid data is available from the UPI-41A (in Output Data Bus BuffI er) f ``EN FLAGS'' has been executed P25 becomes the IBF (Input Buffer Full) pin A ``1'' written to P25 4 enables the IBF pin (the pin outputs the inverse of
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DMA Handshake Capability
EN DMA Op Code 0E5H
1
1
1
0
0
1
0
1
D7 D0 6 The RESET input on the 8742 includes a 2-stage synchronizer to support reliable reset operation 7 for 12 MHz operation When EA is enabled on the 8742 the program counter is placed on Port 1 and the lower three bits of Port 2 (MSB e P22 LSB e P10) On the 8742 this information is multiplexed with PORT DATA (see port timing diagrams at end of this data sheet)
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8742
APPLICATIONS
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Figure 3 8088-8742 Interface
Figure 4 8048H-8742 Interface
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Figure 5 8742-8243 Keyboard Scanner
Figure 6 8742 80-Column Matrix Printer Interface
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5
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