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8XC152JA JB JC JD UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER
X 8K Factory Mask Programmable ROM Available
Y Y
Superset of 80C51 Architecture Multi-Protocol Serial Communication I O Port (2 048 Mbps 2 4 Mbps Max) SDLC HDLC Only CSMA CD and SDLC HDLC User Definable Protocols Full Duplex Half Duplex MCS -51 Compatible UART 16 5 MHz Maximum Clock Frequency Multiple Power Conservation Modes 64KB Program Memory Addressing
Y Y Y Y Y Y Y Y Y
64KB Data Memory Addressing 256 Bytes On-Chip RAM Dual On-Chip DMA Channels Hold Hold Acknowledge Two General Purpose Timer Counters 5 or 7 I O Ports 56 Special Function Registers 11 Interrupt Sources Available in 48 Pin Dual-in-Line Package and 68 Pin Surface Mount PLCC Package
(See Packaging Spec Order
231369)
Y Y Y Y Y
The 80C152 which is based on the MCS -51 CPU is a highly integrated single-chip 8-bit microcontroller designed for cost-sensitive high-speed serial communications It is well suited for implementing Integrated Services Digital Networks (ISDN) emerging Local Area Networks and user defined serial backplane applications In addition to the multi-protocol communication capability the 80C152 offers traditional microcontroller S features for peripheral I O interface and control ilicon implementations are much more cost effective than multi-wire cables found in board level parallel-toserial and serial-to-parallel converters The 83C152 contains in silicon all the features needed for the serialto-parallel conversion Other 83C152 benefits include 1) better noise immunity through differential signaling or fiber optic connections 2) data integrity utilizing the standard designed in CRC checks and 3) better modularia ty of hardware and software designs All of these cost network parameter and real estate improvements pply to 83C152 serial links between boards or systems and 83C152 serial links on a single board
I Other brands and names are the property of their respective owners nformation in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata O COPYRIGHT INTEL CORPORATION 1995 ctober 1989 Order Number 270431-003
8XC152JA JB JC JD
270431 2 270431 1
270431 3
Figure 1 Connection Diagrams
2
8XC152JA JB JC JD
On 80C152JB JD Only
270431 18
Figure 2 Block Diagram
3
8XC152JA JB JC JD
PSEN is used in conjunction with Port 5 and Port 6 program memory operations EPSEN functions like PSEN during program memory operation but supports Port 5 and Port 6 EPSEN is the read strobe to E external program memory for Port 5 and Port 6 PSEN is activated twice during each machine cycle unless an external data memory operation occurs on Port(s) 0 and Port 2 When external data memory is accessed the second activation of EPSEN is sk N ipped which is the same as when using PSEN ote that data memory fetches cannot be made W through Ports 5 and 6 hen EBEN is high and EA is low all program memory operations take place via Ports 5 and 6 The high byte of the address goes out on Port 6 and the low byte is output on Port 5 ALE is still used to latch the address on Port 5 Next the op code is read on Port 5 The timing is the same as when using Ports 0 and 2 E for external program memory operations
80C152JB JD General Description
The 80C152JB JD is a ROMless extension of the 80C152 Universal Communication controller The 80C152JB has the same five 8-bit I O ports of the 80C152 plus an additional two 8-bit I O ports Port 5 and Port 6 The 80C152JB JD also has two additional control pins EBEN (EPROM Bus ENable) and EPSEN (EPROM bus Program Store ENable) W EN selects the functionality of Port 5 and Port 6 B hen EBEN is low these ports are strictly I O similar to Port 4 The SFR location for Port 5 is 91H and Port 6 is 0A1H This means Port 5 and Port 6 are not bit addressable With EBEN low all program memory fetches take place via Port 0 and Port 2 (The 80C152 is a ROMless only product) When EBEN is high Port 5 and Port 6 form an address data bus called the E-Bus (EPROM-Bus) for program memory T operations
able 1 Program Memory Fetches EBEN 0 0 1 1 EA 0 1 0 1 Program Fetch via P0 P2 NA P5 P6 P5 P6 P0 P2 PSEN Active NA Inactive Inactive Active EPSEN Inactive NA Active Active Inactive Comments Addresses 0 0FFFFH Invalid Combination Addresses 0 0FFFFH Addresses 0 1FFFH Addresses t 2000H
Table 2 8XC152 Product Differences ROMless Version 80C152JA 8 CSMA CD and HDLC SDLC HDLC SDLC Only ROM Version Available PLCC and DIP PLCC Only 5I O Ports 7I 0 Ports
(83C152JA) (83C152JC)
80C152JB 80C152JC N
0C152JD
OTES e options available 0 standard frequency range 3 5 MHz to 12 MHz 0 ``b1'' frequency range 3 5 MHz to 16 5 MHz
VSS Circuit ground Port 0 Port 0 is an 8-bit open drain bidirectional I O port As an output port each pin can sink 8 LS TTL inputs Port 0 pins that have 1s written to them float and in that state can be used as high-impedance inputs P ort 0 is also the multiplexed low-order address and data bus during accesses to external program memory if EBEN is pulled low During accesses to external Data Memory Port 0 always emits the low-order address byte and serves as the multiplexed daP bus In these applications it uses strong internal pullups when emitting 1s ta ort 0 also outputs the code bytes during program verification External pullups are required during program verification Port 1 Port 1 is an 8-bit bidirectional I O port with internal pullups Port 1 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 1 pins that are externally being pulled low will source cuP ent (IIL on the data sheet) because of the internal pullups rr ort 1 also serves the functions of various special features of the 8XC152 as listed below P in P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 Name GRXD GTXD DEN TXC RXC HLD HLDA Alternate Function GSC data input pin GSC data output pin GSC enable signal for an external driver GSC input pin for external transmit clock GSC input pin for external receive clock DMA hold input output DMA hold acknowledge input output
29-36
41-48
1 0- 17 14-16 18 19 23-25
Port 2 Port 2 is an 8-bit bidirectional I O port with internal pullups Port 2 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 2 pins that are externally being pulled low will source cuP ent (IIL on the data sheet) because of the internal pullups rr ort 2 emits the high-order address byte during fetches from external Program Memory if EBEN is pulled low During accesses to external Data Memory that use 16bit addresses (MOVX DPTR and DMA operations) Port 2 emits the high-order adDress byte In these applications it uses strong internal pullups when emitting 1s d P uring accesses to external Data Memory that use 8-bit addresses (MOVX Ri) oPt 2 emits the contents of the P2 Special Function Register r ort 2 also receives the high-order address bits during program verification Port 3 Port 3 is an 8-bit bidirectional I O port with internal pullups Port 3 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are externally being pulled low will source cuP ent (IIL on the data sheet) because of the pullups rr ort 3 also serves the functions of various special features of the MCS-51 Family as listed below P in P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 Name RXD TXD INT0 INT1 T0 T1 WR RD Alternate Function Serial input line Serial output line External Interrupt 0 External Interrupt 1 Timer 0 external input Timer 1 external input External Data Memory Write strobe External Data Memory Read strobe
