|
Details, datasheet, quote on part number:8XC196KB
| |
Datasheet text preview:
8XC196KB ADVANCED 16-BIT CHMOS MICROCONTROLLER ROMless OR ROM
Automotive
Y Y Y Y Y Y Y Y Y Y Y
b 40
C to a 125 C Ambient
Y
232 Bytes of On-Chip Register RAM 8 Kbytes of On-Chip ROM (Optional) High-Performance CHMOS Process Register-to-Register Architecture 10-Bit A D Converter with S H Five 8-Bit I O Ports 28 Interrupt Sources Pulse Width Modulated Output Powerdown and Idle Modes High Speed I O Subsystem
Y Y Y Y Y Y Y Y Y
Dynamically Configurable 8 16-Bit Buswidth Full Duplex Serial Port Dedicated Baud Rate Generator 1 725 ms 16 x 16 Multiply 3 ms 32 16 Divide 16-Bit Watchdog Timer 16-Bit Timer 16-Bit Up Down Counter w Capture Four 16-Bit Software Timers HOLD HOLDA Bus Protocol
The 8XC196KB 16-bit microcontroller comes with 8 Kbytes of on-chip mask programmable ROM or in ROMless versions All devices are high performance members of the 8096 microcontroller family The 8XC196KB is pin-to-pin compatible and uses a true superset of the 8096 instructions Intel's CHMOS process provides a high performance processor along with low power consumption To further reduce power requirements the B processor can be placed into Idle or Powerdown Mode it byte word and some 32-bit operations are available on the 8XC196KB With a 16 MHz oscillator a 16-bit Fddition takes 0 495 ms and the instruction times average 0 375 ms to 1 125 ms in typical applications a our high-speed capture inputs are provided to record times when events occur 4 a 2 high-speed outputs are available for pulse or waveform generation The high-speed output can also generate four software timers or A start an A D conversion Events can be based on the 16-bit timer or a 16-bit up down counter lso provided on-chip are an 8 channel 10-bit A D converter with Sample and Hold a serial port with synchronous asynchronous modes and on-chip baud rate generator a 16-bit watchdog timer pulse width modulated output with prescaler and an on-chip clock failure detect circuitry 2
70679 1
Figure 1 8XC196KB Block Diagram
I Other brands and names are the property of their respective owners nformation in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata F COPYRIGHT INTEL CORPORATION 1995 ebruary 1995 Order Number 270679-005
AUTOMOTIVE 8XC196KB
270679 3
Figure 2 The 8XC196KB Family Nomenclature
ARCHITECTURE
The 8XC196KB is a member of the 8096 family as such has the same architecture and uses the same instruction set as the 8096 Many new features have C been added on the 8CX196KB including PU FEATURES Divide by 2 instead of divide by 3 clock for a 1 5 c performance improvement Faster instructions especially indexed indirect data operations 1 725 ms 16 x 16 multiply with 16 MHz clock (is 6 25 ms on the 8096) Faster interrupt response (almost twice as fast) Powerdown and Idle Modes 6 new instructions 8 new interrupt vectors 6 new interrupt sources PERIPHERAL FEATURES SFR window switching allows read-only SFRs to be written and vice-versa Timer 2 can count up and down by external selection
Timer 2 has an independent capture register on rising edges of (P2 7) HSO line events are stored in a register HSO has CAM lock and CAM clear commands w New baud rate values are needed for serial port Dhich enables higher speeds in all modes o ouble buffered serial port transmit register (before nly receive was double buffered) Serial port receive overrun and framing error detection PWM has a divide by 2 prescaler HOLD HLDA bus protocol THERMAL CHARACTERISTICS PLCC iJA iJC Max Case Temperature 35 C W 12 C W 135 C
NEW INSTRUCTIONS PUSHA PUSHes the PSW IMASK IMASK1 and WSR (used instead of PUSHF when using the new interrupts and registers) POPA POPs the PSW IMASK IMASK1 and WSR (used instead of POPF when using the new interrupts and registers)
2
AUTOMOTIVE 8XC196KB
IDLPD Sets the device into Idle or Powerdown Mode The instruction has the following format IDLPD key (where key e 1 for Idle and key e 2 for Powerdown Illegal keys are processed but no action is taken Compare 2 long direct values Only the direct addressing mode is supported for this instruction and the format follows the CMP format Block move using 2 auto-incrementing pointers and a counter The instruction has the following format BMOV w IPTR wCNT The IPTR is a long word ith the low word being the address of the source and the upper word being the address of the destination wCNT is the number of words to be transferred JNZW S Decrement Jump Not Zero using a word counter The instruction format follows the DJNZ instruction
S ee the Functional Deviations section for details
C MPL B MOV
FR OPERATION All of the registers that were present on the 8096 work the same way as they did except that the baud rate value will be different on the 8XC196KB The new registers shown in the memory map control new functions The most important register is the Window Select Register (WSR) which allows the reading of P the formerly write-only registers and vice-versa ACKAGING Dhe 8XC196KB is available in 68-pin plastic leaded T chip carrier (PLCC) and 68-pin CERQUAD packages Contact your local sales office to determine the exact ordering code for the part desired 2
70679 2
Figure 3 68-Pin PLCC Package
3
AUTOMOTIVE 8XC196KB
PLCC 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
Description ACH7 PO 7 PMD3 ACH6 PO 6 PMD2 ACH2 PO 2 ACH0 PO 0 ACH1 PO 1 ACH3 PO 3 NMI EA VCC VSS XTAL1 XTAL2 CLKOUT BUSWIDTH INST ALE ADV RD AD0 P3 0 AD1 P3 1 AD2 P3 2 AD3 P3 3 AD4 P3 4 AD5 P3 5 AD6 P3 6 AD7 P3 7 AD8 P4 0 AD9 P4 1 AD10 P4 2 AD11 P4 3 AD12 P4 4 AD13 P4 5 AD14 P4 6 AD15 P4 7 T2CLK P2 3
PLCC 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Description READY T2RST P2 4 AINC BHE WRH WR WRL PWM P2 5 P2 7 T2CAPTURE PACT VPP VSS HSO 3 HSO 2 P2 6 P1 7 HOLD P1 6 HLDA P1 5 BREQ HSO 1 HSO 0 HSO 5 HSI 3 SID3 HSO 4 HSI 2 SID2 HSI 1 SID1 HSI 0 SID0 P1 4 P1 3 P1 2 P1 1 P1 0 TXD P2 0 PVER RXD P2 1 PALE RESET EXTINT P2 2 PROG VSS VREF ANGND ACH4 P0 4 PMD0 ACH4 P0 5 PMD1
Figure 4 PLCC Functional Pinouts
4
AUTOMOTIVE 8XC196KB
PIN DESCRIPTIONS
Symbol VCC VSS
REF
Name and Function Main Supply Voltage ( a 5V) Digital Circuit Ground (0V) There are three VSS pins all of which MUST be connected Reference for the A D Converter ( a 5V) VREF is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function Reference Ground for the A D Converter Must be held at nominally the same potential as VSS Programming Voltage for the EPROM Parts It should be a 12 75V for programming This pin w C as VBB on 8X9X-90 parts It is also the timing pin for the return from powerdown circuit onnect this pin with a 1 mF capacitor to VSS and a 1 MX resistor to VCC If this function is not used VPP may be tied to VCC Input of the Oscillator Inverter and the Internal Clock Generator Output of the Oscillator Inverter Output of the Internal Clock Generator The frequency of CLKOUT is frequency It has a 50% duty cycle the oscillator
A NGND V
PP
X TAL1 XTAL2 CLKOUT R ESET B USWIDTH N I MI NST E A
Reset Input to the Chip Input low for at least 4 state times will reset the chip The subsequent low to high transition resynchronizes CLKOUT and commences a 10-state time sequence in which the PSW is cleared a byte is read from 2018H loading the CCB and a jump to location 2080H is executed Input high for normal operation RESET has an internal pullup Input for Bus Width Selection If CCR bit 1 is a one this pin selects the buswidth for the bus cycle in progress If BUSWIDTH is low an 8-bit cycle occurs If BUSWIDTH is high a 16-bit cycle occurs If CCR bit 1 is a 0 the bus is always an 8-bit bus This pin is the TEST pin on the 8X9X-90 parts Systems with TEST tied to VCC need NOT change A positive transition causes an interrupt vector through external memory location 203EH Output High during an External Memory Read Indicates the read is an instruction fetch INST is valid throughout the bus cycle INST is active only during external memory fetches during internal EPROM ROM fetches INST is held low Input for Memory Select (External Access) EA equal to a TTL-high causes memory accesses to locations 2000H through 3FFFH to be directed to on-chip EPROM ROM EA equal to a TTL-low causes accesses to these locations to be directed to off-chip memory EA e a s 12 75V causes execution to begin in the Programming Mode EA has an internal pulldown o it defaults to execute from external memory unless otherwise driven EA is latched at reset Address Latch Enable or Address Valid Output as Selected by CCR Both pin options provide a latch to demultiplex the address from the address data bus When the pin is ADV it goes inactive (high) at the end of the bus cycle ADV can be used as a chip select for external 5 memory ALE ADV is active only during external memory accesses
A LE ADV
|
|
