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Details, datasheet, quote on part number:8xC196MC
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Datasheet text preview:
8XC196MC INDUSTRIAL MOTOR CONTROL MICROCONTROLLER
8 87C196MC 16 Kbytes of On-Chip OTPROM 7C196MC ROM 16 Kbytes of On-Chip Factory-Programmed OTPROM 80C196MC ROMless
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High-Performance CHMOS 16-Bit CPU F 16 Kbytes of On-Chip OTPROM actory-Programmed OTPROM 488 bytes of On-Chip Register RAM Register to Register Architecture Up to 53 I O Lines Peripheral Transaction Server (PTS) with 11 Prioritized Sources Event Processor Array (EPA) 4 High Speed Capture Compare Modules 4 High Speed Compare Modules Extended Temperature Standard
Two 16-Bit Timers with Quadrature Decoder Input 3-Phase Complementary Waveform Generator H 13 Channel 8 10-Bit A D with Sample old with Zero Offset Adjustment H W 14 Prioritized Interrupt Sources Flexible 8- 16-Bit External Bus 1 75 ms 16 x 16 Multiply 3 ms 32 16 Divide Idle and Power Down Modes
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The 8XC196MC is a 16-bit microcontroller designed primarily to control 3 phase AC induction and DC brushless motors The 8XC196MC is based on Intel's MCS 96 16-bit microcontroller architecture and is manufacT tured with Intel's CHMOS process he 8XC196MC has a three phase waveform generator specifically designed for use in ``Inverter'' motor control applications This peripheral allows for pulse width modulation three phase sine wave generation with minimal CPU intervention It generates 3 complementary non-overlapping PWM pulses with resolutions of 0 125 ms (edge trigger) or 0 250 ms (centered) T he 8XC196MC has 16 Kbytes on-chip OTPROM ROM and 488 bytes of on-chip RAM It is available in three N packages PLCC (84-L) SDIP (64-L) and EIAJ QFP (80-L) Oote that the 64-L SDIP package does not include P1 4 P2 7 P5 1 and the CLKOUT pins T perational characteristics are guaranteed over the temperature range of b 40 C to a 85 C he 87C196MC contains 16 Kbytes on-chip OTPROM The 83C196MC contains 16 Kbytes on-chip ROM All references to the 80C196MC also refers to the 83C196MC and 87C196MC unless noted O
TPROM (One Time Programmable Read Only Memory) is the same as EPROM but it comes in an unwindowed package and cannot be erased It is user programmable
I Other brands and names are the property of their respective owners nformation in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata A COPYRIGHT INTEL CORPORATION 1995 pril 1994 Order Number 270946-005
8XC196MC
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C NOTE onnections between the standard I OF orts and the bus are not shown p
igure 1 87C196MC Block Diagram
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8XC196MC
PROCESS INFORMATION
This device is manufactured on PX29 5 a CHMOS III-E process Additional process and reliability information is available in Intel's Components Quality r and Reliability Handbook Order Numbe2 210997
XC196MC Memory Map Description External Memory or I O Internal ROM EPROM or External Memory (Determined by EA) Reserved Must contain FFH (Note 5) PTS Vectors Upper Interrupt Vectors ROM EPROM Security Key
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Address 0FFFFH 06000H 5FFFH 2080H 207FH 205EH 205DH 2040H 203FH 2030H 202FH 2020H 201FH 201CH 201BH 201AH 2019H 2018H 2017H 2014H 2013H 2000H 1FFFH 1F00H 1EFFH 0200H 01FFH 0018H 0017H 0000H
Reserved Must contain FFH (Note 5) Reserved Must Contain 20H (Note 5) CCB1 Reserved Must Contain 20H (Note 5) CCB0 Reserved Must contain FFH (Note 5) Lower Interrupt Vectors
1 EXAMPLE N87C196MC is 84-Lead PLCC OTPROM F6 MHz or complete package dimensional data refer to the N Intel Packaging Handbook (Order Number 240800) 1 OTE EPROMs are available as One Time Programmable F TPROM) only (O
igure 3 The 8XC196MC Family Nomenclature Thermal Characteristics Package Type PLCC QFP SDIP ija 35 C W 56 C W TBD ijc
SFR's 13 C W 12 C W TBD 488 Bytes Register RAM (Note 1) CPU SFR's (Notes 1 3)
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External Memory
All thermal impedance data is approximate for static air conditions at 1W of power dissipation Values will change depending on operation conditions and application See the Intel Packaging Handbook (order number 240800) for a description of Intel's thermal impedance test methodology
1 NOTES Code executed in locations 0000H to 03FFH will be 2 forced external Reserved memory locations must contain 0FFH unless 3 noted 4 Reserved SFR bit locations must contain 0 5 Refer to 8XC196KC for SFR descriptions WARNING Reserved memory locations must not be written or read The contents and or function of these loT cations may change with future revisions of the device herefore a program that relies on one or more of these locations may not function properly 3
8XC196MC
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NOTE T The pin sequence is correct he 64-Lead SDIP package does not include the following pins P1 4 ACH12 P2 7 COMPARE3 P5 1 INST CLKOUT F
igure 2 64-Lead Shrink DIP (SDIP) Package
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8XC196MC
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NOTE C means No Connect Do not connect F ese pins th
igure 3 84-Lead PLCC Package
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