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Part: 8XC196NT
Category:
Microcontrollers
-> CISC->X86/X96 Family
Description: Chmos Microcontroller With 1 MB Linear Address Space
Company: Intel Corporation
Datasheet: Download 8XC196NT datasheet File size : 47 kB
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Datasheet text preview:
8XC196NT CHMOS MICROCONTROLLER WITH 1 MBYTE LINEAR ADDRESS SPACE
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20 MHz Operation High Performance CHMOS 16-Bit CPU Up to 32 Kbytes of On-Chip OTPROM Up to 1 Kbyte of On-Chip Register RAM Up to 512 Bytes of Internal RAM Register-Register Architecture 4 Channel 10-Bit A D with Sample Hold 37 Prioritized Interrupt Sources Up to Seven 8-Bit (56) I O Ports Full Duplex Serial I O Port Dedicated Baud Rate Generator Interprocessor Communication Slave Port Selectable Bus Timing Modes for Flexible External Memory Interfacing
Reg RAM 1K
Y Y
Oscillator Fail Detection Circuitry High Speed Peripheral Transaction Server (PTS) Two Dedicated 16-Bit High-Speed Compare Registers 10 High Speed Capture Compare (EPA) Full Duplex Synchronous Serial I O Port (SSIO) Two Flexible 16-Bit Timer Counters Quadrature Counting Inputs Flexible 8- 16-Bit External Bus (Programmable) Programmable Bus (HOLD HLDA) 1 4 ms 16 x 16 Multiply 2 4 ms 32 16 Divide 68-Pin Package
Code RAM 512 Address Space 1 Mbyte IO 56 EPA 10 AD 4
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Device 8XC196NT
Pins Package 68P PLCC
OTPROM 32K
X e 7 OTPROM Device X e 0 ROMLESS
The 8XC196NT 16-bit microcontroller is a high performance member of the MCS 96 microcontroller family he 8XC196NT is an enhanced 8XC196KR device with 1 Mbyte of linear address space 1000 bytes of register RAM 512 bytes of internal RAM 20 MHz operation and an optional 32 Kbytes of OTPROM Intel's T CHMOS III-E process provides a high performance processor along with low power consumption en high-speed capture compare modules are provided As capture modules event times with 200 ns resolus tion can be recorded and generate interrupts As compare modules events such as toggling of a port pin tarting an A D conversion pulse width modulation and software timers can be generated Events can be based on the timer or up down counter
December 1996
Order Number 272267-005
8XC196NT
272267 1
Figure 1 8XC196NT Block Diagram
PROCESS INFORMATION
This device is manufactured on P629 5 a CHMOS III-E process Additional process and reliability information is available in Intel's Components Quality T and Reliability Handbook Order Number 210997 able 1 Thermal Characteristics Package Type PLCC iJA 36 5 C W iJC 13 C W
All thermal impedance data is approximate for static air conditions at 1W of power dissipation Values will change depending on operation conditions and application See the Intel Packaging Handbook (order number 240800) for a description of Intel's thermal impedance test methodology 2
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F EXAMPLE N87C196NT is 68-Lead PLCC OTPROM or complete package dimensF nal data refer to the Intel Packaging Handbook (Order Number 240800) io
igure 2 The 8XC186NT Familiy Nomenclature
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8XC196NT
8XC196NT Memory Map Address (Note 7) FFFFFFH FFA000H FF9FFFH FF2080H FF207FH FF2000H FF1FFFH FF0600H FF05FFH FF0400H FF03FFH FF0100H FF00FFH FF0000H FEFFFFH 100000H FFFFFH 00A000H 009FFFH 002080H 00207FH 002000H 001FFFH 001FE0H 001FDFH 001F00H 001EFFH 000600H 0005FFH 000400H 0003FFH Register RAM 000100H 0000FFH 000018H 00017H 000000H Register RAM CPU SFR's External Memory Internal OTPROM or External Memory (Determined by EA Pin) RESET at FF2080H Reserved Memory (Internal OTPROM or External Memory) (Determined by EA Pin) External Memory Internal RAM (Identically Mapped into 00400H 005FFH) External Memory Reserved for ICE External Memory for future devices 984 Kbytes External Memory Internal OTPROM or External Memory (Note 1) Reserved Memory (Internal OTPROM or External Memory) (Notes 1 3 and 6) Memory Mapped Special Function Registers (SFR's) Internal Special Function Registers (SFR's) (Note 5) External Memory Internal RAM (Address with Indirect or Indexed Modes) Upper Register File (Address with Indirect or Description
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Indexed Modes or through Windows ) (Note 2) Lower Register File (Address with Direct Indirect or Indexed Modes ) (Notes 2 4)
1 NOTES These areas are mapped internal OTPROM if the REMAP bit (CCB2 2) is set and EA e 5V Otherwise they are external 2 memory 3 Code executed in locations 00000H to 003FFH will be forced external 4 Reserved memory locations must contain 0FFH unless noted 5 Reserved SFR bit locations must be written with 0 6 Refer to 8XC196NT User's Guide and Quick Reference for SFR descriptions T WARNING The contents or functions of reserved memory locations may change with future revisions of the device 7 herefore a program that relies on one or more of these locations may not function properly The 8XC196NT internally uses 24 bit address but only 20 address lines are bonded out allowing 1 Mbyte external address space 3
8XC196NT
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Figure 3 68-Pin PLCC Package Diagram
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8XC196NT
PIN DESCRIPTIONS
Symbol VCC
SS VSS1 VSS1
Name and Function Main supply voltage ( a 5V) Digital circuit ground (0V) There are multiple VSS pins all of which MUST be connected Reference for the A D converter ( a 5V) VREF is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function Programming voltage for the OTPROM parts It should be a 12 5V for programming I t is also the timing pin for the return from powerdown circuit Connect to VCC if powerdown not being used Reference ground for the A D converter Must be held at nominally the same potential as VSS Input of the oscillator inverter and the internal clock generator Output of the oscillator inverter Output of the internal clock generator The frequency is I t has a 50% duty cycle Also LSIO pin the oscillator frequency
V
REF
V
PP
A NGND X XTAL1 PTAL2 2 7 CLKOUT R P ESET 5 7 BUSWIDTH
Reset input to and open-drain output from the chip RESET has an internal pullup Input for bus width selection If CCR bit 1 is a one and CCR1 bit 2 is a one this pin a dyamically controls the Buswidth of the bus cycle in progress If BUSWIDTH is low n 8-bit cycle occurs if BUSWIDTH is high a 16-bit cycle occurs If CCR bit 1 is ``0'' and CCR1 bit 2 is ``1'' all bus cycles are 8-bit if CCR bit 1 is ``1'' and CCR1 bit 2 is ``0'' all bus cycles are 16-bit CCR bit 1 e ``0'' and CCR1 bit 2 e ``0'' is illegal Also an LSIO pin when not used as BUSWIDTH A positive transition causes a non maskable interrupt vector through memory location 203EH Output high during an external memory read indicates the read is an instruction fetch INST is valid throughout the bus cycle INST is active only during external memory fetches during internal OTPROM fetches INST is held low Also LSIO when not INST SLPCS is the Slave Port Chip Select Input for memory select (External Access) EA equal to a high causes memory accesses to locations 0FF2000H through 0FF9FFFH to be directed to on-chip OTPROM EA equal to a low causes accesses to these locations to be directed to off-chip memory EA e a 12 5V causes execution to begin in the Programming Mode EA is latched at reset Bus Hold Input requesting control of the bus Bus Hold acknowledge output indicating release of the bus Bus Request output activated when the bus controller has a pending external memory cycle Address Latch Enable or Address Valid output as selected by CCR Both pin options provide a latch to demultiplex the address from the address data bus When t he pin is ADV it goes inactive (high) at the end of the bus cycle ADV can be used as a chip select for external memory ALE ADV is active only during external memory accesses Also LSIO when not used as ALE SLPADDR is the Slave Port Address Control Input and SLPALE is the Slave Port Address Latch Enable Input Read signal output to external memory RD is active only during external memory reads or LSIO when not used as RD SLPRD is the Slave Port Read Control Input 5
N MI P 5 1 INST SLPCS E A
H HOLD B LDA REQ P 5 0 ALE ADV SLPADDR SLPALE P 5 3 RD SLPRD
Others parts begin by 8x
8X-1
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