|
|
Part: E7500
Category:
Interface and Interconnect
-> Chipsets
Description: Intel E7500 Chipset Datasheet: Intel E7500 Chipset Memory Controller Hub (MCH)
Company: Intel Corporation
Datasheet: Download E7500 datasheet File size : 1486 kB
Request For quote: Find where to buy E7500
Datasheet text preview:
IntelŪ E7500 Chipset
Datasheet IntelŪ E7500 Memory Controller Hub (MCH)
February 2002
Document Number: 290730-001
Information in this document is provided in connection with IntelŪ products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The IntelŪ E7500 chipset MCH component may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. IIntel, Intel NetBurst and the Intel logo are trademarks or registered trademarks of Intel corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. CopyrightĐ 2002, Intel Corporation
2
Datasheet
Contents
1 Introduction ....... 11
1.1 1.2 1.3 1.4 Glossary of Terms ..... 11 Reference Documents........12 IntelŪ E7500 Chipset System Architecture..........12 1.3.1 IntelŪ 82801CA I/O Controller Hub 3-S (ICH3-S)..13 1.3.2 IntelŪ 82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2)..14 IntelŪ E7500 MCH Overview.......14 1.4.1 Processor System Interface .......... 15 1.4.2 Main Memory Interface.........15 1.4.3 Hub Interface_A (HI_A) ........ 15 1.4.4 Hub Interface_BD (HI_BD)........16 1.4.5 MCH Clocking ....... 16 1.4.6 SMBus Interface....16 System Bus Interface Signals ........... 19 DDR Channel A Signals ..... 22 DDR Channel B Signals ..... 23 Hub Interface_A Signals.....24 Hub Interface_B Signals.....25 Hub Interface_C Signals .... 26 Hub Interface_D Signals .... 27 Clocks, Reset, Power, and Miscellaneous Signals ............ 28 Pin States During and After Reset .... 28 Register Terminology ......... 31 Platform Configuration........32 General Routing Configuration Accesses .. 33 3.3.1 Standard PCI Configuration Mechanism ...... 33 3.3.2 Logical PCI Bus 0 Configuration Mechanism ........ 34 3.3.3 Primary PCI Downstream Configuration Mechanism ..... 34 3.3.4 HI_B, HI_C, HI_D Bus Configuration Mechanism .......... 34 Sticky Registers.........35 I/O Mapped Registers ........ 35 3.5.1 CONF_ADDR--Configuration Address Register .. 35 3.5.2 CONF_DATA--Configuration Data Register.........36 DRAM Controller Registers (Device 0, Function 0)............37 3.6.1 VID--Vendor Identification Register (D0:F0) ........ 38 3.6.2 DID--Device Identification Register (D0:F0) ......... 38 3.6.3 PCICMD--PCI Command Register (D0:F0) ......... 39 3.6.4 PCISTS--PCI Status Register (D0:F0) ........ 40 3.6.5 RID--Revision Identification Register (D0:F0) ...... 41 3.6.6 SUBC--Sub-Class Code Register (D0:F0) ........... 41 3.6.7 BCC--Base Class Code Register (D0:F0)............41 3.6.8 MLT--Master Latency Timer Register (D0:F0) ..... 42
2
Signal Description ......... 17
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
3
Register Description ..... 31
3.1 3.2 3.3
3.4 3.5 3.6
Datasheet
3
3.7
HDR--Header Type Register (D0:F0).... 42 SVID--Subsystem Vendor Identification Register (D0:F0) ........... 42 SID--Subsystem Identification Register (D0:F0) .. 43 MCHCFG--MCH Configuration Register (D0:F0).......... 43 MCHCFGNS--MCH Memory Scrub and Initialization Configuration Register (D0:F0).... 45 3.6.14 FDHC--Fixed DRAM Hole Control Register (D0:F0)..... 46 3.6.15 PAM[0:6]--Programmable Attribute Map Registers (D0:F0)......... 47 3.6.16 DRB--DRAM Row Boundary Register (D0:F0) .... 49 3.6.17 DRA--DRAM Row Attribute Register (D0:F0) ...... 50 3.6.18 DRT--DRAM Timing Register (D0:F0) ........ 51 3.6.19 DRC--DRAM Controller Mode Register (D0:F0) .. 52 3.6.20 CLOCK_DIS--CK/CK# Disable Register (D0:F0).......... 53 3.6.21 SMRAM--System Management RAM Control Register (D0:F0) .. 54 3.6.22 ESMRAMC--Extended System Management RAM Control Register (D0:F0) ......... 55 3.6.23 TOLM--Top of Low Memory Register (D0:F0) ..... 56 3.6.24 REMAPBASE--Remap Base Address Register (D0:F0)..... 56 3.6.25 REMAPLIMIT--Remap Limit Address Register (D0:F0)...... 57 3.6.26 SKPD--Scratchpad Data Register (D0:F0)........... 57 3.6.27 DVNP--Device Not Present Register (D0:F0) ...... 58 DRAM Controller Error Reporting Registers (Device 0, Function 1) .......... 59 3.7.1 VID--Vendor Identification Register (D0:F1) ........ 60 3.7.2 DID--Device Identification Register (D0:F1)......... 60 3.7.3 PCICMD--PCI Command Register (D0:F1) ......... 61 3.7.4 PCISTS--PCI Status Register (D0:F1) ........ 61 3.7.5 RID--Revision Identification Register (D0:F1) ...... 62 3.7.6 SUBC--Sub-Class Code Register (D0:F1) ........... 62 3.7.7 BCC--Base Class Code Register (D0:F1)............ 63 3.7.8 MLT--Master Latency Timer Register (D0:F1) ..... 63 3.7.9 HDR--Header Type (D0:F1) ......... 64 3.7.10 SVID--Subsystem Vendor Identification Register (D0:F1) ........... 65 3.7.11 SID--Subsystem Identification Register (D0:F1) .. 65 3.7.12 FERR_GLOBAL--Global Error Register (D0:F1).. 66 3.7.13 NERR_GLOBAL--Global Error Register (D0:F1) .......... 67 3.7.14 HIA_FERR--Hub Interface_A First Error Register (D0:F1) .......... 68 3.7.15 HIA_NERR--Hub Interface_A Next Error Register (D0:F1).......... 69 3.7.16 SCICMD_HIA--SCI Command Register (D0:F1) .......... 70 3.7.17 SMICMD_HIA--SMI Command Register (D0:F1).......... 71 3.7.18 SERRCMD_HIA--SERR Command Register (D0:F1) .. 72 3.7.19 SYSBUS_FERR--System Bus First Error Register (D0:F1)......... 73 3.7.20 SYSBUS_NERR--System Bus Next Error Register (D0:F1)........ 74 3.7.21 SCICMD_SYSBUS--SCI Command Register (D0:F1).. 75 3.7.22 SMICMD_SYSBUS--SMI Command Register (D0:F1) ....... 76 3.7.23 SERRCMD_SYSBUS--SERR Command Register (D0:F1)......... 77 3.7.24 DRAM_FERR--DRAM First Error Register (D0:F1) ...... 78 3.7.25 DRAM_NERR--DRAM Next Error Register (D0:F1) ..... 78 3.7.26 SCICMD_DRAM--SCI Command Register (D0:F1)...... 79 3.7.27 SMICMD_DRAM--SMI Command Register (D0:F1) ..... 79 3.7.28 SERRCMD_DRAM--SERR Command Register (D0:F1).... 80
3.6.9 3.6.10 3.6.11 3.6.12 3.6.13
4
Datasheet
3.8
3.9
3.10 3.11
3.7.29 DRAM_CELOG_ADD--DRAM First Correctable Memory Error Address Register (D0:F1).....80 3.7.30 DRAM_UELOG_ADD--DRAM First Uncorrectable Memory Error Address Register (D0:F1).....81 3.7.31 DRAM_CELOG_SYNDROME--DRAM First Correctable Memory Error Register (D0:F1) .......... 81 HI_B Virtual PCI-to-PCI Bridge Registers (Device 2, Function 0) ..... 82 3.8.1 VID2--Vendor Identification Register (D2:F0) ...... 83 3.8.2 DID2--Device Identification Register (D2:F0) ....... 83 3.8.3 PCICMD2--PCI Command Register (D2:F0) ....... 84 3.8.4 PCISTS2--PCI Status Register (D2:F0) ...... 85 3.8.5 RID2--Revision Identification Register (D2:F0) .... 86 3.8.6 SUBC2--Sub-Class Code Register (D2:F0) ......... 86 3.8.7 BCC2--Base Class Code Register (D2:F0) .......... 87 3.8.8 MLT2--Master Latency Timer Register (D2:F0) ... 87 3.8.9 HDR2--Header Type Register (D2:F0)........88 3.8.10 PBUSN2--Primary Bus Number Register (D2:F0) ........ 88 3.8.11 BUSN2--Secondary Bus Number Register (D2:F0) ...... 89 3.8.12 SUBUSN2--Subordinate Bus Number Register (D2:F0) ..... 89 3.8.13 SMLT2--Secondary Bus Master Latency Timer Register (D2:F0) ........ 90 3.8.14 IOBASE2--I/O Base Address Register (D2:F0)....91 3.8.15 IOLIMIT2--I/O Limit Address Register (D2:F0).....91 3.8.16 SEC_STS2--Secondary Status Register (D2:F0) ......... 92 3.8.17 MBASE2--Memory Base Address Register (D2:F0) ..... 93 3.8.18 MLIMIT2--Memory Limit Address Register (D2:F0) ...... 94 3.8.19 PMBASE2--Prefetchable Memory Base Address Register (D2:F0)......95 3.8.20 PMLIMIT2--Prefetchable Memory Limit Address Register (D2:F0).......95 3.8.21 BCTRL2--Bridge Control Register (D2:F0) .......... 96 HI_B Virtual PCI-to-PCI Bridge Registers (Device 2, Function 1) ..... 97 3.9.1 VID--Vendor Identification Register (D2:F1) ........ 98 3.9.2 DID--Device Identification Register (D2:F1) ......... 98 3.9.3 PCICMD--PCI Command Register (D2:F1) ......... 99 3.9.4 PCISTS--PCI Status Register (D2:F1) ........ 99 3.9.5 RID--Revision Identification Register (D2:F1) .... 100 3.9.6 SUBC--Sub-Class Code Register (D2:F1) ......... 100 3.9.7 BCC--Base Class Code Register (D2:F1)..........101 3.9.8 HDR--Header Type Register (D2:F1)........101 3.9.9 SVID--Subsystem Vendor Identification Register (D2:F1) ......... 102 3.9.10 SID--Subsystem Identification Register (D2:F1) ......... 102 3.9.11 HIB_FERR--Hub Interface_B First Error Register (D2:F1) ........ 103 3.9.12 HIB_NERR--Hub Interface_B Next Error Register (D2:F1)........104 3.9.13 SERRCMD2--SERR Command Register (D2:F1) ...... 105 3.9.14 SMICMD2--SMI Command Register (D2:F1).....106 3.9.15 SCICMD2--SCI Command Register (D2:F1) ..... 107 HI_C Virtual PCI-to-PCI Bridge Registers (Device 3, Function 0,1).........108 3.10.1 DID--Device Identification Register (D3:F0) ....... 108 3.10.2 DID--Device Identification Register (D3:F1) ....... 108 HI_D Virtual PCI-to-PCI Bridge Registers (Device 4, Function 0,1).........109 3.11.1 DID--Device Identification Register (D4:F0) ....... 109 3.11.2 DID--Device Identification Register (D4:F1) ....... 109
Datasheet
5
Others parts begin by e7
E7-1
|
|
|
