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Part: E7501
Category:
Interface and Interconnect
-> Chipsets
Description: Intel E7501 Chipset Memory Controller Hub (MCH)
Company: Intel Corporation
Datasheet: Download E7501 datasheet File size : 1486 kB
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Intel® E7501 Chipset Memory Controller Hub (MCH)
Datasheet
December 2002
Document Number: 251927-001
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® E7501 chipset MCH component may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Intel Xeon, and the Intel logo are trademarks or registered trademarks of Intel corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2002, Intel Corporation
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Intel® E7501 Chipset MCH Datasheet
Contents
1 Introduction ....... 13
1.1 1.2 1.3 Terminology......... 13 Reference Documents........14 Intel® E7501 Chipset System Architecture..........14 System Bus Interface Signals ........... 19 DDR Channel A Signals ..... 22 DDR Channel B Signals ..... 23 Hub Interface_A Signals.....24 Hub Interface_B Signals.....25 Hub Interface_C Signals .... 26 Hub Interface_D Signals .... 27 Clocks, Reset, Power, and Miscellaneous Signals ............ 28 Register Terminology ......... 29 Platform Configuration........30 3.2.1 Standard PCI Configuration Mechanism ...... 31 PCI Configuration Cycle Routing.......31 3.3.1 Logical PCI Bus 0 Configuration Mechanism ........ 32 3.3.2 Primary PCI Downstream Configuration Mechanism ..... 32 3.3.3 HI_B, HI_C, HI_D Bus Configuration Mechanism .......... 32 I/O Mapped Registers ........ 33 3.4.1 CONFIG_ADDRESS--Configuration Address Register ...... 33 3.4.2 CONFIG_DATA--Configuration Data Register.....33 Chipset Host Controller Registers (Device 0, Function 0)..34 3.5.1 VID--Vendor Identification Register (D0:F0) ........ 35 3.5.2 DID--Device Identification Register (D0:F0) ......... 35 3.5.3 PCICMD--PCI Command Register (D0:F0) ......... 36 3.5.4 PCISTS--PCI Status Register (D0:F0) ........ 37 3.5.5 RID--Revision Identification Register (D0:F0) ...... 38 3.5.6 SUBC--Sub-Class Code Register (D0:F0) ........... 38 3.5.7 BCC--Base Class Code Register (D0:F0)............38 3.5.8 MLT--Master Latency Timer Register (D0:F0) ..... 39 3.5.9 HDR--Header Type Register (D0:F0)....39 3.5.10 SVID--Subsystem Vendor Identification Register (D0:F0) ........... 39 3.5.11 SID--Subsystem Identification Register (D0:F0) .. 40 3.5.12 CAPPTR--Capabilities Pointer Register (D0:F0)..40 3.5.13 MCHCAP--MCH Capabilities Structure Register (D0:F0) ............ 41 3.5.14 MCHCFG--MCH Configuration Register (D0:F0) .......... 41 3.5.15 MCHCFGNS--MCH Configuration Register (D0:F0) ..... 43 3.5.16 FDHC--Fixed DRAM Hole Control Register (D0:F0) ..... 43 3.5.17 PAM[6:0]--Programmable Attribute Map Registers (D0:F0).........44 3.5.18 DRB[0:7]--DRAM Row Boundary Register (D0:F0) ...... 46 3.5.19 DRA[3:0]--DRAM Row Attribute Register (D0:F0) ........ 47
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Signal Description ......... 17
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8
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Register Description ..... 29
3.1 3.2 3.3
3.4 3.5
Intel® E7501 Chipset MCH Datasheet
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3.6
3.7
DRT--DRAM Timing Register (D0:F0) ........ 48 DRC--DRAM Controller Mode Register (D0:F0) .. 50 CKDIS--CK / CK# Disable Register (D0:F0) ........ 51 CFGCTL--Configuration Control Register (D0:F0)........ 52 SMRAMC--System Management RAM Control Register (D0:F0)......... 53 ESMRAMC--Extended System Management RAM Control Register (D0:F0).... 54 3.5.26 TOLM--Top of Low Memory Register (D0:F0) ..... 55 3.5.27 REMAPBASE--Remap Base Address Register (D0:F0)..... 55 3.5.28 REMAPLIMIT--Remap Limit Address Register (D0:F0)...... 56 3.5.29 SKPD--Scratchpad Data Register (D0:F0)........... 56 3.5.30 DVNP--Device Not Present Register (D0:F0) ...... 57 Host RASUM Controller Registers (Device 0, Function 1) .......... 58 3.6.1 VID--Vendor Identification Register (D0:F1) ........ 59 3.6.2 DID--Device Identification Register (D0:F1)......... 59 3.6.3 PCICMD--PCI Command Register (D0:F1) ......... 60 3.6.4 PCISTS--PCI Status Register (D0:F1) ........ 61 3.6.5 RID--Revision Identification Register (D0:F1) ...... 61 3.6.6 SUBC--Sub-Class Code Register (D0:F1) ........... 62 3.6.7 BCC--Base Class Code Register (D0:F1)............ 62 3.6.8 MLT--Master Latency Timer Register (D0:F1) ..... 62 3.6.9 HDR--Header Type Register (D0:F1).... 63 3.6.10 SVID--Subsystem Vendor Identification Register (D0:F1) ........... 63 3.6.11 SID--Subsystem Identification Register (D0:F1) .. 63 3.6.12 FERR_GLOBAL--First Global Error Register (D0:F1)... 64 3.6.13 NERR_GLOBAL--Next Global Error Register (D0:F1).. 65 3.6.14 HIA_FERR--HI_A First Error Register (D0:F1) .... 66 3.6.15 HIA_NERR--HI_A Next Error Register (D0:F1).... 67 3.6.16 SCICMD_HIA--SCI Command Register (D0:F1) .......... 68 3.6.17 SMICMD_HIA--SMI Command Register (D0:F1).......... 69 3.6.18 SERRCMD_HIA--SERR Command Register (D0:F1) .. 70 3.6.19 SYSBUS_FERR--System Bus First Error Register (D0:F1)......... 71 3.6.20 SYSBUS_NERR-- System Bus Next Error Register (D0:F1)....... 72 3.6.21 SCICMD_SYSBUS--SCI Command Register (D0:F1).. 73 3.6.22 SMICMD_SYSBUS--SMI Command Register (D0:F1) ....... 74 3.6.23 SERRCMD_SYSBUS--SERR Command Register (D0:F1)......... 75 3.6.24 DRAM_FERR--DRAM First Error Register (D0:F1) ...... 76 3.6.25 DRAM_NERR--DRAM Next Error Register (D0:F1) ..... 76 3.6.26 SCICMD_DRAM--SCI Command Register (D0:F1)...... 77 3.6.27 SMICMD_DRAM--SMI Command Register (D0:F1) ..... 77 3.6.28 SERRCMD_DRAM--SERR Command Register (D0:F1).... 78 3.6.29 DRAM_CELOG_ADD--DRAM First Correctable Memory Error Address Register (D0:F1)..... 78 3.6.30 DRAM_UELOG_ADD--DRAM First Uncorrectable Memory Error Address Register (D0:F1)..... 79 3.6.31 DRAM_CELOG_SYNDROME--DRAM First Correctable Memory Error Syndrome Register (D0:F1) .......... 79 Hub Interface_B PCI-to-PCI Bridge Registers (Device 2, Function 0) ....... 80 3.7.1 VID--Vendor Identification Register (D2:F0) ........ 81 3.7.2 DID--Device Identification Register (D2:F0)......... 81
3.5.20 3.5.21 3.5.22 3.5.23 3.5.24 3.5.25
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Intel® E7501 Chipset MCH Datasheet
3.8
3.9 3.10
3.7.3 PCICMD--PCI Command Register (D2:F0) ......... 82 3.7.4 PCISTS--PCI Status Register (D2:F0) ........ 83 3.7.5 RID--Revision Identification Register (D2:F0) ...... 84 3.7.6 SUBC--Sub-Class Code Register (D2:F0) ........... 84 3.7.7 BCC--Base Class Code Register (D2:F0)............84 3.7.8 MLT--Master Latency Timer Register (D2:F0) ..... 85 3.7.9 HDR--Header Type Register (D2:F0)....85 3.7.10 PBUSN--Primary Bus Number Register (D2:F0) .......... 86 3.7.11 SBUSN--Secondary Bus Number Register (D2:F0)......86 3.7.12 SUBUSN--Subordinate Bus Number Register (D2:F0).......87 3.7.13 SMLT--Secondary Bus Master Latency Timer Register (D2:F0) .......... 87 3.7.14 IOBASE--I/O Base Address Register (D2:F0)......88 3.7.15 IOLIMIT--I/O Limit Address Register (D2:F0).......88 3.7.16 SEC_STS--Secondary Status Register (D2:F0) .. 89 3.7.17 MBASE--Memory Base Address Register (D2:F0) ....... 90 3.7.18 MLIMIT--Memory Limit Address Register (D2:F0) ........ 91 3.7.19 PMBASE--Prefetchable Memory Base Address Register (D2:F0)........92 3.7.20 PMLIMIT--Prefetchable Memory Limit Address Register (D2:F0).........92 3.7.21 BCTRL--Bridge Control Register (D2:F0) ............ 93 Hub Interface_B PCI-to-PCI Bridge Error Reporting Registers (Device 2, Function 1) .......... 94 3.8.1 VID--Vendor Identification Register (D2:F1) ........ 95 3.8.2 DID--Device Identification Register (D2:F1) ......... 95 3.8.3 PCICMD--PCI Command Register (D2:F1) ......... 96 3.8.4 PCISTS--PCI Status Register (D2:F1) ........ 96 3.8.5 RID--Revision Identification Register (D2:F1) ...... 97 3.8.6 SUBC--Sub-Class Code Register (D2:F1) ........... 97 3.8.7 BCC--Base Class Code Register (D2:F1)............98 3.8.8 HDR--Header Type Register (D2:F1)....98 3.8.9 SVID--Subsystem Vendor Identification Register (D2:F1) ........... 99 3.8.10 SID--Subsystem Identification Register (D2:F1) .. 99 3.8.11 HIB_FERR--HI_B First Error Register (D2:F1) .. 100 3.8.12 HIB_NERR--HI_B Next Error Register (D2:F1)..101 3.8.13 SERRCMD--SERR Command Register (D2:F1) ........ 102 3.8.14 SMICMD--SMI Command Register (D2:F1).......103 3.8.15 SCICMD--SCI Command Register (D2:F1) ....... 104 Hub Interface_C PCI-to-PCI Bridge Registers (Device 3, Function 0, 1) .......... 105 Hub Interface_D PCI-to-PCI Bridge Registers (Device 4, Function 0, 1) .......... 107 System Memory Spaces .. 109 4.1.1 VGA and MDA Memory Spaces..111 4.1.2 PAM Memory Spaces.........111 4.1.3 ISA Hole Memory Space .... 112 4.1.4 TSEG SMM Memory Space ........ 112 4.1.5 I/O APIC Memory Space .... 113 4.1.6 System Bus Interrupt Memory Space.........113 4.1.7 High SMM Memory Space .......... 113 4.1.8 Device 2 Memory and Prefetchable Memory ...... 113 4.1.9 Device 3 Memory and Prefetchable Memory ...... 114
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System Address Map...........109
4.1
Intel® E7501 Chipset MCH Datasheet
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