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Part: E7505
Category:
Interface and Interconnect
-> Chipsets
Description: Intel E7505 Chipset Memory Controller Hub (MCH)
Company: Intel Corporation
Datasheet: Download E7505 datasheet File size : 1486 kB
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Intel® E7505 Chipset Memory Controller Hub (MCH)
Datasheet
December 2002
Document Number: 251932-002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® E7505 chipset MCH may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel, Intel Xeon, Intel NetBurst and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2001-2002 Intel Corporation
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Intel® E7505 Chipset MCH Datasheet
Contents
1 Introduction ....... 15
1.1 1.2 1.3 Terminology......... 15 Reference Documents........16 Intel® E7505 Chipset System Architecture..........18 Host Interface Signals ........ 23 DDR Channel A Signals ..... 26 DDR Channel B Signals ..... 29 Hub Interface_A Signals.....32 Hub Interface_B Signals.....32 AGP Interface Signals ........ 33 2.6.1 AGP Arbitration Signals........33 2.6.2 AGP Address / Data Signals ......... 34 2.6.3 AGP Command/Control Signals....35 Clocks, Reset, and Miscellaneous Signals..........37 Strap Signals ............. 38 Register Nomenclature and Access Attributes....39 PCI Configuration Space Access ...... 40 3.2.1 PCI Bus Configuration Mechanism ........ 41 General Routing Configuration Accesses .. 41 3.3.1 Logical PCI Bus #0 Configuration Mechanism ...... 42 3.3.2 Primary PCI Downstream Configuration Mechanism ..... 42 3.3.3 HI_B Bus Configuration Mechanism ...... 42 3.3.4 AGP Bus Configuration Mechanism.......43 I/O Mapped Registers ........ 43 3.4.1 CONFIG_ADDRESS--Configuration Address Register ...... 44 3.4.2 CONFIG_DATA--Configuration Data Register.....44 Chipset Host Controller Registers (Device 0, Function 0)..45 3.5.1 VID--Vendor Identification Register (D0:F0) ........ 46 3.5.2 DID--Device Identification Register (D0:F0) ......... 46 3.5.3 PCICMD--PCI Command Register (D0:F0) ......... 47 3.5.4 PCISTS--PCI Status Register (D0:F0) ........ 48 3.5.5 RID--Revision Identification Register (D0:F0) ...... 49 3.5.6 SUBC--Sub-Class Code Register (D0:F0) ........... 49 3.5.7 BCC--Base Class Code Register (D0:F0)............49 3.5.8 MLT--Master Latency Timer Register (D0:F0) ..... 50 3.5.9 HDR--Header Type Register (D0:F0)....50 3.5.10 APBASE--Aperture Base Configuration Register (D0:F0) ........... 51 3.5.11 SVID--Subsystem Vendor Identification Register (D0:F0) ........... 52 3.5.12 SID--Subsystem Identification Register (D0:F0) .. 52 3.5.13 CAPPTR--Capabilities Pointer Register (D0:F0)..52 3.5.14 CAPID--Product Specific Capability Identifier Register (D0:F0)...53 3.5.15 MCHCFG--MCH Configuration Register (D0:F0) .......... 54
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Signal Description ......... 21
2.1 2.2 2.3 2.4 2.5 2.6
2.7 2.8
3
Register Description ..... 39
3.1 3.2 3.3
3.4 3.5
Intel® E7505 Chipset MCH Datasheet
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3.6
PAM[0:6]--Programmable Attribute Map Registers (D0:F0)......... 56 DRB--DRAM Row Boundary Register (D0:F0) .... 58 DRA--DRAM Row Attribute Register (D0:F0) ...... 60 DRT--DRAM Timing Register (D0:F0) ........ 61 DRC--DRAM Controller Mode Register (D0:F0) .. 64 REROTC--Receive Enable Reference Output Timing Control Register (D0:F0)66 3.5.22 CLOCK_DIS--CK/CK# Clock Disable Register (D0:F0)...... 66 3.5.23 DDR_CNTL--DDR Memory Control Register (D0:F0)... 67 3.5.24 SMRAM--System Management RAM Control Register (D0:F0) .. 68 3.5.25 ESMRAMC--Extended System Management RAM Control Register (D0:F0)69 3.5.26 ACAPID--AGP Capability Identifier Register (D0:F0).... 70 3.5.27 AGPSTAT--AGP Status Register (D0:F0)............ 70 3.5.28 AGPCMD--AGP Command Register (D0:F0) ...... 72 3.5.29 AGPCTRL--AGP Control Register (D0:F0) .......... 73 3.5.30 APSIZE--Aperture Size Register (D0:F0).... 74 3.5.31 ATTBASE--Aperture Translation Table Register (D0:F0) ............ 75 3.5.32 AMTT--AGP MTT Control Register (D0:F0)......... 75 3.5.33 LPTT--AGP Low Priority Transaction Time Register (D0:F0) ...... 76 3.5.34 TOLM--Top of Low Memory Register (D0:F0) ..... 77 3.5.35 REMAPBASE--Remap Base Address Register (D0:F0)..... 77 3.5.36 REMAPLIMIT--Remap Limit Address Register (D0:F0)...... 78 3.5.37 SKPD--Scratch Pad Data Register (D0:F0) ......... 78 3.5.38 DVNP--Device Not Present Register (D0:F0) ...... 78 Chipset Host RAS Controller Registers (Device 0, Function 1)79 3.6.1 VID--Vendor Identification Register (D0:F1) ........ 80 3.6.2 DID--Device Identification Register (D0:F1)......... 80 3.6.3 PCICMD--PCI Command Register (D0:F1) ......... 81 3.6.4 PCISTS--PCI Status Register (D0:F1) ........ 81 3.6.5 RID--Revision Identification Register (D0:F1) ...... 82 3.6.6 SUBC--Sub-Class Code Register (D0:F1) ........... 82 3.6.7 BCC--Base Class Code Register (D0:F1)............ 82 3.6.8 MLT--Master Latency Timer Register (D0:F1) ..... 83 3.6.9 HDR--Header Type Register (D0:F1).... 83 3.6.10 SVID--Subsystem Vendor Identification Register (D0:F1) ........... 83 3.6.11 SID--Subsystem Identification Register (D0:F1) .. 83 3.6.12 FERR_GLOBAL--Global First Error Register (D0:F1)... 84 3.6.13 NERR_GLOBAL--Global Next Error Register (D0:F1).. 85 3.6.14 HIA_FERR--HI_A First Error Register (D0:F1) .... 86 3.6.15 HIA_NERR--HI_A Next Error Register (D0:F1).... 87 3.6.16 SCICMD_HIA--SCI Command Register (D0:F1) .......... 87 3.6.17 SMICMD_HIA--SMI Command Register (D0:F1).......... 88 3.6.18 SERRCMD_HIA--SERR Command Register (D0:F1) .. 88 3.6.19 SB_FERR--System Bus First Error Register (D0:F1) ... 89 3.6.20 SB_NERR--System Bus Next Error Register (D0:F1)... 90 3.6.21 SCICMD_SB--SCI Command Register (D0:F1)... 91 3.6.22 SMICMD_SB--SMI Command Register (D0:F1).. 92 3.6.23 SERRCMD_SB--SERR Command Register (D0:F1).... 93
3.5.16 3.5.17 3.5.18 3.5.19 3.5.20 3.5.21
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Intel® E7505 Chipset MCH Datasheet
3.6.24 3.6.25 3.6.26 3.6.27 3.6.28 3. 6.29
3.7
3.8
DRAM_FERR--DRAM First Error Register (D0:F1) ...... 94 DRAM_NERR--DRAM Next Error Register (D0:F1) ..... 94 SCICMD_DRAM --SCI Command Register (D0:F1) ..... 95 SMICMD_DRAM--SMI Command Register (D0:F1) ..... 95 SERRCMD_DRAM--SEER Command Register (D0:F1) .... 96 DRAM_CELOG_ADD--DRAM First Correctable Memory Error Address Register (D0:F1)96 3.6.30 DRAM_UELOG_ADD--DRAM First Uncorrectable Memory Error Address Register (D0:F1)97 3.6.31 DRAM_CELOG_SYNDROME--DRAM First Correctable Memory Error Register (D0:F1) ..... 97 PCI-to-AGP Bridge Registers (Device 1, Function 0).........98 3.7.1 VID1--Vendor Identification Register (D1:F0) ...... 99 3.7.2 DID1--Device Identification Register (D1:F0) ....... 99 3.7.3 PCICMD1--PCI Command Register (D1:F0) ..... 100 3.7.4 PCISTS1--PCI Status Register (D1:F0) .... 101 3.7.5 RID1--Revision Identification Register (D1:F0) .. 102 3.7.6 SUBC1--Sub-Class Code Register (D1:F0) ....... 102 3.7.7 BCC1--Base Class Code Register (D1:F0) ........ 102 3.7.8 MLT1--Master Latency Timer (Scratch Pad) Register (D1:F0) .. 103 3.7.9 HDR1--Header Type Register (D1:F0)......103 3.7.10 APBASELO--AGP Aperture Base Address Register (D1:F0) .... 104 3.7.11 PBUSN1--Primary Bus Number Register (D1:F0) ...... 105 3.7.12 SBUSN1--Secondary Bus Number Register (D1:F0)..105 3.7.13 SUBUSN1--Subordinate Bus Number Register (D1:F0) ............ 105 3.7.14 SMLT1--Secondary Bus Master Latency Timer Register (D1:F0) ...... 106 3.7.15 IOBASE1--I/O Base Address Register (D1:F0)..106 3.7.16 IOLIMIT1--I/O Limit Address Register (D1:F0)...107 3.7.17 SSTS1--Secondary Status Register (D1:F0) ..... 108 3.7.18 MBASE1--Memory Base Address Register (D1:F0) ... 109 3.7.19 MLIMIT1--Memory Limit Address Register (D1:F0) .... 110 3.7.20 PMBASE1--Prefetchable Memory Base Address Register (D1:F0)....111 3.7.21 PMLIMIT1--Prefetchable Memory Limit Address Register (D1:F0).....112 3.7.22 CAPPTR--Capabilities Pointer Register (D1:F0).........112 3.7.23 BCTRL1--Bridge Control Register (D1:F0) ........ 113 3.7.24 ERRCMD1--Error Command Register (D1:F0) .. 114 3.7.25 ERRSTS1--Error Status Register (D1:F0) ......... 115 3.7.26 AGPCAPID1--AGP Capability Identifier Register (D1:F0) ......... 115 3.7.27 AGPSTAT1--AGP Status Register (D1:F0)........116 3.7.28 AGPCMD--AGP Command Register (D1:F0) .... 117 3.7.29 AGPCTRL1--AGP Control Register (D1:F0) ...... 119 3.7.30 APSIZE1--AGP Aperture Size Register (D1:F0) ......... 120 3.7.31 ATTBASE1--AGP GART Pointer Register (D1:F0) ..... 121 Hub Interface_B PCI-to-PCI Bridge Registers (Device 2, Function 0) ..... 122 3.8.1 VID2--Vendor Identification Register (D2:F0) .... 123 3.8.2 DID2--Device Identification Register (D2:F0) ..... 123 3.8.3 PCICMD2--PCI Command Register (D2:F0) ..... 124 3.8.4 PCISTS2--PCI Status Register (D2:F0) .... 125 3.8.5 RID2--Revision Identification Register (D2:F0) .. 126 3.8.6 SUBC2--Sub-Class Code Register (D2:F0) ....... 126
Intel® E7505 Chipset MCH Datasheet
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