|Category||Microprocessors => CISC => X86 Family|
|Datasheet||Download INTEL386SXSA datasheet
|Static Intel386TM CPU Core Integrated Memory Management Unit
Low Power Consumption Operating Power Supply - 25 and 33 MHz - 40 MHz Operating Frequency = 40 MHz = 33 MHz = 25 MHz Clock Freeze Mode Allows Clock Stopping at Any Time
(MMU) Virtual Memory Support Optional On-chip Paging 4 Levels of Hardware-Enforced Protection MMU Fully Compatible with 80286 and Intel386 DX Processors Virtual 8086 Mode Allows Execution of 8086 Software in a Protected and Paged System
16-, 32-bit Data Types 8 General Purpose 32-bit Registers Runs Intel386 Architecture Software in a Cost-effective, 16-bit Hardware Environment Runs Same Applications and Operating Systems as the Intel386 SX and Intel386 DX Processors Object Code Compatible with 80186, 80286, and Intel386 Processors TTL-Compatible Inputs
16 Megabyte Physical 64 Terabyte Virtual 4 Gigabyte Maximum Segment Size Numerics Support Intel387TM SX and Intel387TM SL Math CoprocessorsHigh Speed CHMOS Technology 100-Pin Plastic Quad Flatpack Package
Two-clock Bus Cycles Address Pipelining Allows Use of Slower, Inexpensive Memories
The Intel386TM SXSA embedded microprocessor 5-volt, 32-bit, fully static CPU with a 16-bit external data bus and a 24-bit external address bus. The Intel386 SXSA CPU brings the vast software library of the Intel386 architecture to embedded systems. It provides the performance benefits of 32-bit programming with the cost savings associated with 16-bit hardware systems. The Intel386 SXSA microprocessor is manufactured on Intel's 0.8-micron CHMOS V process. This process provides high performance and low power consumption for power-sensitive applications. Figure 3 and Figure 4 illustrate the flexibility of low power devices with respect to temperature and frequency relationships.
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringe-ment of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information contained herein supersedes previously published specifications on these devices from Intel. Copyright© INTEL Corporation, 2002 June 2002 Order Number: 272419-004
Segmentation Unit 32 Effective Address Bus 32 Effective Address Bus 3-Input Adder Descriptor 32 Register Limit and Attribute PLA Protection Test UnitAddress Driver Pipeline/ Bus Size Control MUX/ Transceivers
M/IO#, D/C# W/R#, LOCK# ADS#, NA# READY#
Status Multiply/ Flags Divide Register File
Instruction Decoder Code 3-Decoded Stream Instruction Queue 32 Instruction Predecode Dedicated ALU BusPrefetcher/ Limit Checker 16-Byte Code Queue Instruction Prefetch
D0 Vss HLDA HOLD Vss NA# READY# Vcc Vss CLK2 ADS# BLE# A1 BHE# NC Vcc Vss M/IO# D/C# W/R#
LOCK# NC FLT# NC Vcc RESET BUSY# Vss ERROR# PEREQ NMI Vcc INTR Vss Vcc NC Vcc Vss
|Some Part number from the same manufacture Intel Corporation|
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