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Details, datasheet, quote on part number:N28F001BX-B150
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Datasheet text preview:
1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
28F001BX-T 28F001BX-B 28F001BN-T 28F001BN-B
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High-Integration Blocked Architecture One 8 KB Boot Block w Lock Out Two 4 KB Parameter Blocks One 112 KB Main Block 100 000 Erase Program Cycles Per Block Simplified Program and Erase Automated Algorithms via On-Chip Write State Machine (WSM) SRAM-Compatible Write Interface Deep Power-Down Mode 0 05 mA ICC Typical 0 8 mA IPP Typical 12 0V g 5% VPP
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High-Performance Read 70 75 ns 90 ns 120 ns 150 ns Maximum Access Time 5 0V g 10% VCC Hardware Data Protection Feature Erase Write Lockout during Power Transitions Advanced Packaging JEDEC Pinouts 32-Pin PDIP 32-Lead PLCC TSOP ETOX TM II Nonvolatile Flash Technology EPROM-Compatible Process Base High-Volume Manufacturing Experience Extended Temperature Options
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Intel's 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with features that simplify write and allow block erase These devices aid the system designer by combining the functions of several components into one making boot block flash an innovative alternative to EPROM and EEPROM or battery-backed static RAM Many new and existing designs can take advantage of the 28F001BX's integration of blocked architecture automated electrical reprogramming and standard processor T interface he 28F001BX-B and 28F001BX-T are 1 048 576 bit nonvolatile memories organized as 131 072 bytes of 8 bits They are offered in 32-pin plastic DIP 32-lead PLCC and 32-lead TSOP packages Pin assignment conform to JEDEC standards for byte-wide EPROMs These devices use an integrated command port and state machine for simplified block erasure and byte reprogramming The 28F001BX-T's block locations provide compatibility with microprocessors and microcontrollers that boot from high memory such as Intel's M t CS -186 family 80286 i386 TM i486 TM i860 TM and 80960CA With exactly the same memory segmentation she 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory uch as Intel's MCS-51 MCS-196 80960KX and 80960SX families All other features are identical and unless T otherwise noted the term 28F001BX can refer to either device throughout the remainder of this document he boot block section includes a reprogramming write lock out feature to guarantee data integrity It is designed to contain secure code which will bring up the system minimally and download code to the other locations of the 28F001BX Intel's 28F001BX employs advanced CMOS circuitry for systems requiring highperformance access speeds low power consumption and immunity to noise Its access time provides no-WAIT-state performance for a wide range of microprocessors and microcontrollers A deep-powerdown mode lowers power consumption to 0 25 mW typical through VCC crucial in laptop computer handheld instrumentation and other low-power applications The RP power control input also provides absolute data protecM tion during system powerup or power loss anufactured on Intel's ETOX process base the 28F001BX builds on years of EPROM experience to yield the higheNlevels of quality reliability and cost-effectiveness st
OTE The 28F001BN is equivalent to the 28F001BX
I Other brands and names are the property of their respective owners nformation in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata N COPYRIGHT INTEL CORPORATION 1995 ovember 1995 Order Number 290406-007
28F001BX-T 28F001BX-B
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Figure 1 28F001BX Block Diagram Table 1 Pin Description Symbol A0 A16 D Q0 DQ7 C E R P
INPUT INPUT
Type INPUT INPUT OUTPUT
Name and Function ADDRESS INPUTS for memory addresses Addresses are internally latched during a write cycle DATA INPUTS OUTPUTS Inputs data and commands during memory write cycles outputs data during memory Status Register and Identifier read cycles The data pins are active high and float to tri-state off when the chip is deselected or the outputs are disabled Data is internally latched during a write cycle CHIP ENABLE Activates the device's control logic input buffers decoders and sense amplifiers CE is active low CE high deselects the memory device and reduces power consumption to standby levels POWERDOWN Puts the device in deep powerdown mode RP is active low R P high gates normal operation RP e VHH allows programming of the boot block RP also locks out erase or write operations when active low providing data protection during power transitions RP active resets internal automation Exit from deep powerdown sets device to Read Array mode OUTPUT ENABLE Gates the device's outputs through the data buffers during a read cycle OE is active low OE e VHH (pulsed) allows programming of the boot block WRITE ENABLE Controls writes to the Command Register and array blocks WE is active low Addresses and data are latched on the rising edge of the WE pulse ERASE PROGRAM POWER SUPPLY for erasing blocks of the array or programming bytes of each block Note With VPP k VPPL max memory contents cannot be altered DEVICE POWER SUPPLY (5V g 10%) GROUND
O E W E VPP V
CC INPUT INPUT
GND 2
28F001BX-T 28F001BX-B
28F010 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 290406 2
28F010 VCC N WE C A14 A13 A8 A9 A11 A OE
10 D CE Q7 DQ6 DQ5 DQ4 DQ3
Figure 2 DIP Pin Configuration
28F010 A11 A9 A8 A13 A14 NC V WE VPP A16 A15 A12 A7 A6 A5 A4
CC
28F010
A OE D CE Q7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 10
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Figure 3 TSOP Lead Configuration
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