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Details, datasheet, quote on part number:N80C186EA20
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Datasheet text preview:
80C186EA 80C188EA AND 80L186EA 80L188EA 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
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80C186 Upgrade for Power Critical Applications Fully Static Operation True CMOS Inputs and Outputs
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Integrated Feature Set Static 186 CPU Core Power Save Idle and Powerdown Modes Clock Generator 2 Independent DMA Channels 3 Programmable 16-Bit Timers Dynamic RAM Refresh Control Unit Programmable Memory and Peripheral Chip Select Logic Programmable Wait State Generator Local Bus Controller System-Level Testing Support (High Impedance Test Mode) Sp2 ed Versions Available (5V) e 5 MHz (80C186EA25 80C188EA25) 20 MHz (80C186EA20 80C188EA20) 13 MHz (80C186EA13 80C188EA13)
Sp1 ed Versions Available (3V) e 3 MHz (80L186EA13 80L188EA13) 8 MHz (80L186EA8 80L188EA8) Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I O Supports 80C187 Numeric Coprocessor Interface (80C186EA only) Av6 ilable in the Following Packages a 8-Pin Plastic Leaded Chip Carrier (PLCC) 80-Pin EIAJ Quad Flat Pack (QFP) 80-Pin Shrink Quad Flat Pack (SQFP) Available in Extended Temperature Range ( b 40 C to a 85 C)
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The 80C186EA is a CHMOS high integration embedded microprocessor The 80C186EA includes all of the features of an ``Enhanced Mode'' 80C186 while adding the additional capabilities of Idle and Powerdown Modes In Numerics Mode the 80C186EA interfaces directly with an 80C187 Numerics 2 oprocessor C
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I Other brands and names are the property of their respective owners nformation in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata O
ctober 1995 COPYRIGHT
INTEL CORPORATION 1995
Order Number 272432-003
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80C186EA 80C188EA 80L186EA 80L188EA
80C186EA 80C188EA AND 80L186EA 80L188EA 16-Bit High Integration Embedded Processor
CONTENTS
INTRODUCTION 80C186EA CORE ARCHITECTURE Bus Interface Unit Clock Generator 80C186EA PERIPHERAL ARCHITECTURE Interrupt Control Unit Timer Counter Unit DMA Control Unit Chip-Select Unit Refresh Control Unit Power Management 80C187 Interface (80C186EA Only) ONCE Test Mode DIFFERENCES BETWEEN THE 80C186XL AND THE 80C186EA Pinout Compatibility Operating Modes TTL vs CMOS Inputs Timing Specifications PACKAGE INFORMATION Prefix Identification Pin Descriptions 80C186EA Pinout PAGE
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CONTENTS
PACKAGE THERMAL SPECIFICATIONS ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Recommended Connections DC SPECIFICATIONS ICC versus Frequency and Voltage PDTMR Pin Delay Calculation AC SPECIFICATIONS AC Characteristics 80C186EA20 13 AC Characteristics 80L186EA13 8 Relative Timings AC TEST CONDITIONS AC TIMING WAVEFORMS DERATING CURVES RESET BUS CYCLE WAVEFORMS EXECUTION TIMINGS INSTRUCTION SET SUMMARY REVISION HISTORY ERRATA
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80C186EA 80C188EA 80L186EA 80L188EA
P NOTE in names in parentheses apply to the 80C186EA 80L188EA
Figure 1 80C186EA 80C188EA Block Diagram 3
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