|
Details, datasheet, quote on part number:P28F010-150
| |
Datasheet text preview:
28F010 1024K (128K x 8) CMOS FLASH MEMORY
Y
Flash Electrical Chip-Erase 1 Second Typical Chip-Erase Quick Pulse Programming Algorithm 10 ms Typical Byte-Program 2 Second Chip-Program 100 000 Erase Program Cycles 12 0V g 5% VPP High-Performance Read 65 ns Maximum Access Time CMOS Low Power Consumption 10 mA Typical Active Current 50 mA Typical Standby Current 0 Watts Data Retention Power Integrated Program Erase Stop Timer
Y
Y
Command Register Architecture for Microprocessor Microcontroller Compatible Write Interface Noise Immunity Features g10% VCC Tolerance Maximum Latch-Up Immunity through EPI Processing ETOX TM Nonvolatile Flash Technology EPROM-Compatible Process Base High-Volume Manufacturing Experience JEDEC-Standard Pinouts 32-Pin Plastic Dip 32-Lead PLCC 32-Lead TSOP
(See Packaging Spec Order
231369)
Y
Y Y Y
Y
Y
Y
Y
Y
Extended Temperature Options
Intel's 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read write random access nonvolatile memory The 28F010 adds electrical chip-erasure and reprogramming to familiar EPROM technology Memory contents can be rewritten in a test socket in a PROM-programmer socket onboard during subassembly test in-system during final test and in-system after-sale The 28F010 increases T memory flexibility while contributing to time and cost savings he 28F010 is a 1024 kilobit nonvolatile memory organized as 131 072 bytes of 8 bits Intel's 28F010 is offered in 32-pin plastic dip or 32-lead PLCC and TSOP packages Pin assignments conform to JEDEC E standards for byte-wide EPROMs xtended erase and program cycling capability is designed into Intel's ETOX (EPROM Tunnel Oxide) process technology Advanced oxide processing an optimized tunneling structure and lower electric field combine to extend reliable cycling beyond that of traditional EEPROMs With the 12 0V VPP supply the 28F010 performs 100 000 erase and program cycles well within the time limits of the Quick Pulse Programming and Quick Erase I algorithms ntel's 28F010 employs advanced CMOS circuitry for systems requiring high-performance access speeds low power consumption and immunity to noise Its 65 nanosecond access time provides no-WAIT-state performance for a wide range of microprocessors and microcontrollers Maximum standby current of 100 mA translates into power savings when the device is deselected Finally the highest degree of latch-up protection is achieved through Intel's unique EPI processing Prevention of latch-up is provided for stresses up to 100 mA on W address and data pins from b 1V to VCC a 1V ith Intel's ETOX process base the 28F010 builds on years of EPROM experience to yield the highest levels of quality reliability and cost-effectiveness
I Other brands and names are the property of their respective owners nformation in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata N COPYRIGHT INTEL CORPORATION 1995 ovember 1995 Order Number 290207-010
28F010
290207 1
Figure 1 28F010 Block Diagram Table 1 Pin Description Symbol A0 A16 D Q 0 DQ 7 C E O E W E
INPUT INPUT INPUT
Type INPUT INPUT OUTPUT
Name and Function ADDRESS INPUTS for memory addresses Addresses are internally latched during a write cycle o DATA INPUT OUTPUT Inputs data during memory write cycles utputs data during memory read cycles The data pins are active high and float to tri-state OFF when the chip is deselected or the outputs are disabled Data is internally latched during a write cycle d CHIP ENABLE Activates the device's control logic input buffers ecoders and sense amplifiers CE is active low CE high deselects the memory device and reduces power consumption to standby levels OUTPUT ENABLE Gates the devices output through the data buffers during a read cycle OE is active low WRITE ENABLE Controls writes to the control register and the array rite enable is active low Addresses are latched on the falling edge and data is latched on the rising edge of the WE pulse Note With VPP s 6 5V memory contents cannot be altered ERASE PROGRAM POWER SUPPLY for writing the command register erasing the entire array or programming bytes in the array DEVICE POWER SUPPLY (5V g 10%) GROUND NO INTERNAL CONNECTION to device Pin may be driven or left floating
V
PP
V
CC
VSS NC 2
28F010
28F010
290207 3
290207 2
290207 17
290207 18
Figure 2 28F010 Pin Configurations
3
|
|
