|
Details, datasheet, quote on part number:PA28F800BVT120
| |
Datasheet text preview:
E
n n n n n
ADVANCE INFORMATION
SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT
28F200B5, 28F400B5, 28F800B5, 28F004B5
SmartVoltage Technology Smart 5 Flash: 5 V Reads, 5 V or 12 V Writes Increased Programming Throughput at 12 V VPP Very High-Performance Read 2-, 4-Mbit: 60 ns Access Time 8-Mbit: 70 ns Access Time x8 or x8/x16-Configurable Data Bus Low Power Consumption Max 60 mA Read Current at 5 V Auto Power Savings: <1 mA Typical Standby Current Optimized Array Blocking Architecture 16-KB Protected Boot Block Two 8-KB Parameter Blocks 96-KB and 128-KB Main Blocks Top or Bottom Boot Locations Extended Temperature Operation 40 °C to +85 °C Industry-Standard Packaging 40, 48-Lead TSOP, 44-Lead PSOP
n n
Extended Block Erase Cycling 100,000 Cycles at Commercial Temp 10,000 Cycles at Extended Temp Hardware Data Protection Feature Absolute Hardware-Protection for Boot Block Write Lockout during Power Transitions Automated Word/Byte Program and Block Erase Command User Interface Status Registers Erase Suspend Capability SRAM-Compatible Write Interface Reset/Deep Power-Down Input Provides Low-Power Mode and Reset for Boot Operations Pinout Compatible 2, 4, and 8 Mbit ETOXTM Flash Technology 0.6 µ ETOX IV Initial Production 0.4 µ ETOX V Later Production
n
n n n n
n n
Intel's Smart 5 boot block flash memory family provides 2-, 4-, and 8-Mbit memories featuring high-density, low-cost, nonvolatile, read/write storage solutions for a wide range of applications. Their asymmetricallyblocked architecture, flexible voltage, and extended cycling provide highly flexible components suitable for embedded code execution applications, such as networking infrastructure and office automation. Based on Intel's boot block architecture, the Smart 5 boot block memory family enables quick and easy upgrades for designs that demand state-of-the-art technology. This family of products comes in industrystandard packages: the 40-lead TSOP for very space-constrained 8-bit applications, 48-lead TSOP, ideal for board-constrained higher-performance 16-bit applications, and the rugged, easy to handle 44-lead PSOP.
December 1997
Order Number: 290599-004
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F200B5, 28F400/004B5, 28F800B5 may contain design defects or errors known are errata. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725 or visit Intel's website at http://www.intel.com
COPYRIGHT © INTEL CORPORATION 1997, 1998 CG-041493
*Third-party brands and names are the property of their respective owners.
E
SMART 5 BOOT BLOCK MEMORY FAMILY
CONTENTS
PAGE PAGE 4.0 DESIGN CONSIDERATIONS ......24 4.1 Power Consumption ..24 4.1.1 Active Power ......24 4.1.2 Automatic Power Savings (APS) .........24 4.1.3 Standby Power ...25 4.1.4 Deep Power-Down Mode............25 4.2 Power-Up/Down Operation.......25 4.2.1 RP# Connected to System Reset ........25 4.3 Board Design ............25 4.3.1 Power Supply Decoupling...........25 4.3.2 VPP Trace on Printed Circuit Boards...25 5.0 ELECTRICAL SPECIFICATIONS.........26 5.1 Absolute Maximum Ratings ......26 5.2 Operating Conditions..........26 5.3 Capacitance .....27 5.4 DC Characteristics--Commercial and Extended Temperature......27 5.5 AC Characteristics--Read Operations-- Commercial and Extended Temperature ...31 5.6 Erase and Program Timings--Commercial and Extended Temperature .....32 5.7 AC Characteristics--Write Operations-- Commercial and Extended Temperature ...33 6.0 ORDERING INFORMATION..35 7.0 ADDITIONAL INFORMATION .....36 APPENDIX A: Write State Machine: CurrentNext State Chart .........37 APPENDIX B: Product Block Diagram.....38
1.0 INTRODUCTION ............ 5 1.1 New Features in the Smart 5 Memory Products ...... 5 1.2 Product Overview........5 2.0 PRODUCT DESCRIPTION......6 2.1 Pin Descriptions .......... 6 2.2 Pinouts.........8 2.3 Memory Blocking Organization..........10 2.3.1 One 16-KB Boot Block.......10 2.3.2 Two 8-KB Parameter Blocks.......10 2.3.3 Main Blocks - One 96-KB + Additional 128-KB Blocks...10 3.0 PRINCIPLES OF OPERATION ............ 13 3.1 Bus Operations ......... 13 3.1.1 Read....13 3.1.2 Output Disable....14 3.1.3 Standby ..... 14 3.1.4 Word/Byte Configuration....14 3.1.5 Deep Power-Down/Reset ........... 14 3.1.6 Write....14 3.2 Modes of Operation...16 3.2.1 Read Array ......... 16 3.2.2 Read Identifier .... 16 3.2.3 Read Status Register .. 16 3.2.4 Word/Byte Program ..... 17 3.2.5 Block Erase ........ 17 3.3 Boot Block Locking ... 23 3.3.1 VPP = VIL for Complete Protection ....... 24 3.3.2 WP# = VIL for Boot Block Locking ....... 24 3.3.3 RP# = VHH or WP# = VIH for Boot Block Unlocking .......... 24 3.3.4 Note for 8-Mbit 44-PSOP Package ...... 24
ADVANCE INFORMATION
3
|
|
