|
Details, datasheet, quote on part number:UPI-42AH
| |
| Part: | UPI-42AH |
| Category: | Communication => Telephony => Line Interface |
| Description: | Universal Peripheral Interface 8-bit Slave Microcontroller |
| Company: | Intel Corporation |
| Datasheet: | Download UPI-42AH datasheet File size : 280 kB |
| Request For quote: | Find where to buy UPI-42AH
|
| |
Datasheet text preview:
UPI-41AH 42AH UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER
Y Y
UPI-41 6 MHz UPI-42 12 5 MHz Pin Software and Architecturally Compatible with all UPI-41 and UPI-42 Products 8-Bit CPU plus ROM OTP EPROM RAM I O Timer Counter and Clock in a Single Package 2048 x 8 ROM OTP 256 x 8 RAM on UPI-42 1024 x 8 ROM OTP 128 x 8 RAM on UPI-41 8-Bit Timer Counter 18 Programmable I O Pins One 8-Bit Status and Two Data Registers for Asynchronous Slave-toMaster Interface DMA Interrupt or Polled Operation Supported
Y
Fully Compatible with all Intel and Most Other Microprocessor Families Interchangeable ROM and OTP EPROM Versions Expandable I O Sync Mode Available Over 90 Instructions 70% Single Byte Available in EXPRESS Standard Temperature Range inteligent Programming Algorithm Fast OTP Programming Available in 40-Lead Plastic and 44Lead Plastic Leaded Chip Carrier Packages
(See Packaging Spec Order Package Type P and N
240800-001)
Y
Y
Y Y Y
Y
Y
Y
Y
Y
Y
The Intel UPI-41AH and UPI-42AH are general-purpose Universal Peripheral Interfaces that allow the designer T to develop customized solutions for peripheral device control I hey are essentially ``slave'' microcontrollers or microcontrollers with a slave interface included on the chip nterface registers are included to enable the UPI device to function as a slave peripheral controller in the MCS T Modules and iAPX family as well as other 8- 16- and 32-bit systems o allow full user flexibility the program memory is available in ROM and One-Time Programmable EPROM (OTP) All UPI-41AH and UPI-42AH devices are fully pin compatible for easy transition from prototype to production level designs 2
10393 2
Figure 1 DIP Pin Configuration
210393 3
Figure 2 PLCC Pin Configuration
November 1994
Order Number 210393-008
UPI-41AH 42AH
210393 1
Figure 3 Block Diagram
UPI PRODUCT MATRIX
UPI Device 8042AH 8242AH 742AH 8041AH 741AH 1K 1K ROM 2K 2K 2K OTP EPROM RAM 256 256 256 128 128 12 5V 12 5V Programming Voltage
THE INTEL 8242
As shown in the UPI-42 product matrix the UPI-42 will be offered as a pre-programmed 8042 with sevT eral software vendors' keyboard controller firmware he current list of available 8242 versions include keyboard controller firmware from both Phoenix Technologies Ltd IBM and Award Software Inc he 8242 is programmed with Phoenix Technologies Ltd keyboard controller firmware for AT-compatible systems This keyboard controller is fully compatible with all AT-compatible operating systems and applications The 8242PC also contains Phoenix Technologies Ltd firmware This keyboard controller C
provides support for AT PS 2 and most EISA platforms as well as PS 2-style mouse support for either T AT or PS 2 platforms he Intel 8242BB is programmed with IBM's keyboard controller firmware The 8242BB provides an off the shelf keyboard and auxiliary device controller T for AT PS 2 EISA and PCI architectures he 8242WA contains Award Software Inc firmware This device provides at AT-compatible keyboard controller for use in IBM PC AT compatible computers The 8242WB contains a version of Award Software Inc firmware that provides PS 2 style mouse support in addition to the standard features of the 8242WA
2 ontact factory for current code revision available in all versions of the 8242 product lines
UPI-41AH 42AH
Table 1 Pin Description
Symbol DIP Pin No 1 39 PLCC Pin Type No 2 43 I Name and Function
TEST 0 TEST 1
X TAL 1 XTAL 2 RESET S S C S E A R D A
0
TEST INPUTS Input pins which can be directly tested using conditional branch instructions FREQUENCY REFERENCE TEST 1 (T1) also functions as the event timer input (under software control) TEST 0 (T0) is used during PROM programming and ROM EPROM verification It is also used during Sync Mode to reset the instruction state to S1 and synchronize the internal clock to PH1 See the Sync Mode Section INPUTS Inputs for a crystal LC or an external timing signal to determine the internal oscillator frequency RESET Input used to reset status flip-flops and to set the program counter to zero ESET is also used during EPROM programming and verification SINGLE STEP Single step input used in conjunction with the SYNC output to step the Trogram through each instruction (EPROM) This should be tied to a 5V when not used p his pin is also used to put the device in Sync Mode by applying 12 5V to it CHIP SELECT Chip select input used to select one UPI microcomputer out of several connected to a common data bus EXTERNAL ACCESS External access input which allows emulation testing and ROM EPROM verification This pin should be tied low if unused READ I O read input which enables the master CPU to read data and status words from the OUTPUT DATA BUS BUFFER or status register COMMAND DATA SELECT Address Input used by the master processor to indicate whether byte transfer is data (A0 e 0 F1 is reset) or command (A0 e 1 F1 is set) A0 e 0 during program and verify operations WRITE I O write input which enables the master CPU to write data and command words to the UPI INPUT DATA BUS BUFFER OUTPUT CLOCK Output signal which occurs once per UPI instruction cycle SYNC can be used as a strobe for external circuitry it is also used to synchronize single step operation DATA BUS Three-state bidirectional DATA BUS BUFFER lines used to interface the UPI microcomputer to an 8-bit master system data bus PORT 1 8-bit PORT 1 quasi-bidirectional I O lines P10 P17 access the signature row and security bit PORT 2 8-bit PORT 2 quasi-bidirectional I O lines The lower 4 bits (P20 P23) interface directly to the 8243 I O expander device and contain address and data information during PORT 4 7 access The upper 4 bits (P24 P27) can be programmed to provide interrupt Request and DMA Handshake capability Software control can configure P24 as Output Buffer Full (OBF) interrupt P25 as Input Buffer Full (IBF) interrupt P26 as DMA Request (DRQ) and P27 as DMA ACKnowledge (DACK) DROGRAM Multifunction pin used as the program pulse input during PROM programming P T uring I O expander access the PROG pin acts as an address data strobe to the 8243 his pin should be tied high if unused POWER a5V main power supply pin POWER a5V during normal operation a12 5V during programming operation Low power standby supply pin GROUND Circuit ground potential 3
2 3 4 5
3 4 5 6
I I I
6 7 8 9
7 8 9 10
I I I I
W R S YNC D
0 D7 P US) (B
10 11
11 13
I O
12 19 14 21
IO IO IO
10 P17 27 34 30 33
35 38 P20 P27 21 24 24 27 35 38 39 42
P ROG V VCC
DD
25
28
IO
40 26 20
44 29 22
V
SS
|
|
