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Details, datasheet, quote on part number:UPI-452
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Datasheet text preview:
UPI-452 CHMOS PROGRAMMABLE I O PROCESSOR
83C452 - 8K c 8 Mask Programmable Internal ROM 80C452 - External ROM EPROM
Y
83C452 80C452 3 5 to 14 MHz Clock Rate Software Compatible with the MCS-51 Family 128-Byte Bi-Directional FIFO Slave Interface Two DMA Channels 256 c 8-Bit Internal RAM
Y Y Y Y
Two 16-Bit Timer Counters Boolean Processor Bit Addressable RAM 8 Interrupt Sources Programmable Full Duplex Serial Channel 64K Program Memory Space 64K Data Memory Space 68-Pin PGA and PLCC
(See Packaging Spec Order
231369)
Y
Y
Y
Y Y Y
Y Y
34 Additional Special Function Registers 40 Programmable I O Lines
Y
Y
The Intel UPI-452 (Universal Peripheral Interface) is a 68 pin CHMOS Slave I O Processor with a sophisticated bi-directional FIFO buffer interface on the slave bus and a two channel DMA processor on-chip The UPI-452 is the newest member of Intel's UPI family of products It is a general-purpose slave I O Processor that allows T the designer to grow a customized interface solution he UPI-452 contains a complete 80C51 with twice the on-chip data and program memory The sophisticated slave FIFO module acts as a buffer between the UPI-452 internal CPU and the external host CPU To both the external host and the internal CPU the FIFO module looks like a bi-directional bottomless buffer that can both read and write data The FIFO manages the transfer of data independent of the UPI-452 core CPU and T generates an interrupt or DMA request to either CPU host or internal as a FIFO service request he FIFO consists of two channels the Input FIFO and the Output FIFO The division of the FIFO module array 128 bytes between Input channel and Output channel is programmable by the user Each FIFO byte A has an additional logical ninth bit to distinguish between a data byte and a Data Stream Command byte dditionally Immediate Commands allow direct interrupt driven bi-directional communication between the T UPI-452 internal CPU and external host CPU bypassing the FIFO Ahe on-chip DMA processor allows high speed data transfers from one writeable memory space to another s many as 64K bytes can be transferred in a single DMA operation Three distinct memory spaces may be used in DMA operations Internal Data Memory External Data Memory and the Special Function Registers (including the FIFO IN FIFO OUT and Serial Channel Special Functions Registers)
I Other brands and names are the property of their respective owners nformation in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata N COPYRIGHT INTEL CORPORATION 1996 ovember 1994 Order Number 231428-006
UPI-452
231428 1
Figure 1 Architectural Block Diagram
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UPI-452
231428 2
Figure 1 Architectural Block Diagram (Continued)
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