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Part: IRMD22141SS
Category:
Description: High Current Gate Driver For ac or Brushless DC Motors With Integrated Desaturation Detection Circuit With Active Bias. (ECONO2-6PACK ...
Company: International Rectifier Corp.
Datasheet: Download IRMD22141SS datasheet File size : 52 kB
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Datasheet text preview:
ADVANCE DATA
Data Sheet No. PD60213
IR2214SS/IR22141SS
HALF-BRIDGE GATE DRIVER IC
Features
· · · · · · · ·
Floating channel up to +1200V Soft overcurrent shutdown Synchronization signal to synchronize shut down with the other phases Integrated desaturation detection circuit Two stage turn on output for di/dt control Separate pull-up/pull-down output drive pins Matched delay outputs Under voltage lockout with hysteresis band
Product Summary
VOFFSET 1200V max. IO+/- (typ.) 2.0 A / 3.0A VOUT 10.4V - 20V Deadtime matching (max) 75nsec Deadtime (typ) 330nsec Desat blanking time (typ) 3µsec DSH,DSL input voltage threshold (typ) 8.0V Soft shutdown time (typ) 9.6µsec
Description
LIN
IR2214SR2214 141SS I S/IR22
The IR2214SS/IR22141SS) is a gate driver suited to drive a single half bridge in power switching applications. The high gate driving capability (2A source, 3A sink) and the low quiescent current enable bootstrap supply techniques in medium power systems. The IR2214SS/IR22141SS driver features full short circuit protection by means of the power transistor desaturation detection. The IR2214SS/IR22141SS manages all the half-bridge faults by turning off smoothly the desaturated transistor through the dedicated soft shut down pin, therefore preventing over-voltages and reducing EM emissions. In multi-phase system IR2214SS/IR22141SS drivers communicate using a dedicated local network (SY_FLT and FAULT/SD signals) to properly manage phase-to-phase short circuits. The system controller may force shutdown or read device fault state through the 3.3 V compatible CMOS I/O pin (FAULT/SD). To improve the signal immunity from DC-bus noise, the control and power ground use d e d i c a t e d pins enabling l o w - s i d e emitter current sensing as well. Under voltage conditions in floating and low VCC VB 15 V voltage circuits are managed HOP independently. HON
HIN SSDH DSH VS
Package
24-Lead SSOP
DC+
Typical Connection
(Refer to Lead Assignments for correct pin configuration). This/ These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
DC BUS (1200V)
uP, Control
FAULT/SD FLT_CLR SY_FLT
Motor
LOP LON SSDL DSL COM
VSS
DC-
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1
IR2214/IR22141(SS)
Absolute Maximum Ratings
ADVANCE DATA
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSS, all currents are defined positive into any lead The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
VS VB VHO VCC COM VLO VIN VFLT VDSH VDSL dVs/dt PD Rth J A TJ TS TL High side offset voltage
Definition
High side floating supply voltage High side floating output voltage (HOP, HON and SSDH) Low side and logic fixed supply voltage Power ground Low side output voltage (LOP, LON and SSDL) Logic input voltage (HIN, LIN and FLT_CLR) FAULT input/output voltage (FAULT/SD and SY_FLT) High side DS input voltage Low side DS input voltage Allowable offset voltage slew rate Package power dissipation @ TA +25°C Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds)
Min.
VB - 25 -0.3 VS - 0.3 -0.3 VCC - 25 VCOM -0.3 -0.3 -0.3 VB -25 VCC - 25 -- -- -- -- -55 --
Max.
VB + 0.3 1225 VB + 0.3 25 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VB + 0.3 VCC + 0.3 50 1.5 65 150 150 300
Units
V
V/ns W
°C/W
°C
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters are absoute voltages referenced to VSS. The VS offset rating is tested with all supplies biased at 15V differential.
Symbol
VB VS VHO VLO VCC COM VIN VFLT VDSH VDSL TA
Definition
High side floating supply voltage (Note 1) High side floating supply offset voltage High side output voltage (HOP, HON and SSDH) Low side output voltage (LOP, LON and SSDL) Low side and logic fixed supply voltage (Note 1) Power ground Logic input voltage (HIN, LIN and FLT_CLR) Fault input/output voltage (FAULT/SD and SY_FLT) High side DS pin input voltage Low side DS pin input voltage Ambient temperature
Min.
VS + 11.5 Note 2 VS VCOM 11.5 -5 0 0 VB - 20 VCC - 20 -40
Max.
VS + 20 1200 VS + 20 VCC 20 5 VCC VCC VB VCC 125
Units
V
°C
Note 1: While internal circuitry is operational below the indicated supply voltages, the UV lockout disables the output drivers if the UV thresholds are not reached. Note 2: Logic operational for VS from VSS-5 to VSS+1200V. Logic state held for VS from VSS-5V to VSS-VBS. (Please refer to the Design Tip DT97-3 for more details).
2
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ADVANCE DATA
Static Electrical Characteristics
IR2214/IR22141(SS)
VCC = 15 V, VSS = COM = 0 V, VS = 0 ÷ 1200 V and TA = 25 oC unless otherwise specified.
P in: V C C , V SS , V B , VS
Symbol VCCUV+ VCCUVVCCUVH VBSUV+ VBSUVVBSUVH ILK IQBS IQCC Definition Vcc supply undervoltage positive going threshold Vcc supply undervoltage negative going threshold Vcc supply undervoltage lockout hysteresis (VB-VS) supply undervoltage positive going threshold (VB-VS) supply undervoltage negative going threshold (VB-VS) supply undervoltage lockout hysteresis Offset supply leakage current Quiescent VBS supply current Quiescent Vcc supply current Min Typ Max Units Test Conditions 9.3 8.7 9.3 8.7 10.2 9.3 0.9 10.2 9.3 0.9 400 0.7 11.4 10.3 11.4 10.3 50 800 2.5
V
VS=0V, VS=1200V VS=0V, VS=1200V VB = VS = 1200V VIN = 0V or 3.3V (No load)
µA mA
comparator VCC/VB UV i n te r n a l si gnal
VCCUV/VBSUV VSS/VS
Figure 1: Undervoltage diagram
Pin: HIN, LIN, FLTCLR, FAULT/SD, SY_FLT
Symbol VIH VIL Definition Logic "1" input voltage Logic "0" input voltage Min 2.0 0.2 -1 Typ 0.4 370 60 60 Max Units Test Conditions 0.8 0 V VCC = VCCUV- to 20V VIN = 3.3V VIN = 0V PW 7 µs ?
Logic input hysteresis IIN+ Logic "1" input bias current IINLogic "0" input bias current RON,FLT FAULT/SD open drain resistance RON,SY SY_FLT open drain resistance
VIHSS
µA
µA
schmitt tri gger HIN/LIN/ FLTCLR 10k i nternal si gnal
VSS
Figure 2: HIN, LIN and FLTCLR diagram www.irf.com 3
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