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Part: 5962D9569401VEC
Category:
Communication
-> DSL (Digital Subscriber Line)
-> DSL Analog Front Ends
Description: Radiation Hardened Single 8/differential 4 Channel CMOS Analog Multiplexers With Active Overvoltage Protection
Company: Intersil Corporation
Datasheet: Download 5962D9569401VEC datasheet File size : 132 kB
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Datasheet text preview:
HS-0548RH, HS-0549RH
Data Sheet August 1999 File Number
3543.3
Radiation Hardened Single 8/Differential 4 Channel CMOS Analog Multiplexers with Active Overvoltage Protection
The HS-0548RH and HS-0549RH are radiation hardened analog multiplexers with Active Overvoltage Protection and guaranteed rON matching. Analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand constant 70V peak-to-peak levels with ±15V supplies and digital inputs will sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from shor t circuiting should multiplexer supply loss occur: each input presents 1k of resistance under this condition. These features make the HS-0548RH and HS-0549RH ideal for use in systems where the analog inputs originate from external equipment or separately powered circuitry. Both devices are fabricated with 44V dielectrically isolated CMOS technology. The HS-0548 is an 8 channel device and the HS-0549 is a 4 channel differential version. If input overvoltage protection is not needed, the HS-0508 and HS-509 multiplexers are recommended. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95694. A "hot-link" is provided on our homepage for downloading. http://www.intersil.com/spacedefense/space.htm
Features
· Electrically Screened to SMD # 5962-95694 · QML Qualified per MIL-PRF-38535 Requirements · Gamma Dose . . . . . . . . . . . . . . . . . . . . . . 1 x 104RAD(Si) · No Latch-Up · No Channel Interaction During Overvoltage · Guaranteed rON Matching · Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . . 44V · Break-Before-Make Switching · Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V · Access Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0µs
Applications
· Data Acquisition Systems · Control Systems · Telemetr y
Pinouts
HS-0548RH GDIP1-T16 (CERDIP) OR CDIP2-T16 (SBDIP) TOP VIEW
AO 1 16 A1 15 A2 14 GND 13 +VSUPPLY 12 IN 5 11 IN 6 10 IN 7 9 IN 8
ENABLE 2 -VSUPPLY 3 IN 1 4 IN 2 5 IN 3 6 IN 4 7
Ordering Information
ORDERING NUMBER 5962D9569401VEA 5962D9569401VEC 5962D9569402VEA 5962D9569402VEC INTERNAL MKT. NUMBER HS1-0548RH-Q HS1B-0548RH-Q HS1-0549RH-Q HS1B-0549RH-Q TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125
OUT 8
HS-0549RH GDIP1-T16 (CERDIP) OR CDIP2-T16 (SBDIP) TOP VIEW
A0 1 ENABLE 2 -VSUPPLY 3 IN 1A 4 IN 2A 5 IN 3A 6 IN 4A 7 OUTA 8 16 A1 15 GND 14 +VSUPPLY 13 IN 1B 12 IN 2B 11 IN 3B 10 IN 4B 9 OUT B
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
HS-0548RH, HS-0549RH Functional Diagrams
HS-0548 HS-0549
IN1 1K IN2 1K DECODER/ DRIVER
OUT
IN1A 1K IN4A 1K IN1B 1K IN4B DECODER/ DRIVER
OUT A
OUT B
1K IN8
OVERVOLTAGE CLAMP AND SIGNAL ISOLATION
5V REF
LEVEL SHIFT
OVERVOLTAGE CLAMP AND SIGNAL ISOLATION
5V REF
LEVEL SHIFT
DIGITAL INPUT PROTECTION
DIGITAL INPUT PROTECTION
A0 A1 A2 EN
A0 A1
EN
HS-0548 TRUTH TABLE A2 X L L L L H H H H A1 X L L H H L L H H A0 X L H L H L H L H EN L H H H H H H H H "ON" CHANNEL NONE 1 2 3 4 5 6 7 8 A1 X L L H H A0 X L H L H
HS-0549 TRUTH TABLE "ON" CHANNEL PAIR NONE 1 2 3 4
EN L H H H H
Switching Waveforms
±10V IN 1 IN 2 THRU IN 7 IN 8 GND -10V VAH OUT VOUT 10K CH 8 ON 200ns/DIV. ± 10V VA INPUT 2V/DIV. CH 1 ON OUTPUT A 5V/DIV.
VAH = 4.0 ADDRESS DRIVE (VA) 1/2VAH +10V -8V tA VAL = 0V OUTPUT A
A2 VA A1 A0 EN
FIGURE 1. ACCESS TIME
2
HS-0548RH, HS-0549RH Switching Waveforms
VAH = 4.0 ADDRESS DRIVE (VA) VA A2 A1 A0 50% 50% OUTPUT EN GND VAH 1K OUTPUT 1V/DIV. +5V IN 1 IN 2 THRU IN 7 IN 8 OUT VA INPUT 2V/DIV. CH 1 ON CH8 ON
(Continued)
0V
VOUT
tOPEN 100ns/DIV.
FIGURE 2. BREAK-BEFORE-MAKE DELAY (tOPEN)
VAH = 4.0 50% 0V OUTPUT 90% 90% tON(EN) tOFF
(EN)
A2 A1
IN 1 IN 2 THRU IN 8
+10V
ENABLE DRIVE 2V/DIV.
A0 EN VA GND OUT 1K CH 1 OFF CH 1 ON OUTPUT 4V/DIV.
100ns/DIV.
FIGURE 3. ENABLE DELAY tON(EN) , tOFF(EN)
Schematic Diagrams
V+ R9 Q1 Q4 D3 LEVEL SHIFTER V+ P P P P P P P P P LEVEL SHIFTED ADDRESS TO DECODE LEVEL SHIFTED ADDRESS TO DECODE R10 TTL REFERENCE CIRCUIT
P OVERVOLTAGE PROTECTION V+ ADD IN. D2 R1 200 D1 VN
N
R2 R5 R3 N R4 N N N N R6 R8 N N N R7
V-
FIGURE 4. ADDRESS INPUT BUFFER AND LEVEL SHIFTER
3
HS-0548RH, HS-0549RH Schematic Diagrams
(Continued)
FROM DECODE P P
+V P P P P
OVERVOLTAGE V+ P
PROTECTION
N
N A0 OR A0 A1 OR A1 A2 OR A2 N
N
N R11 IN 1K D6 D7
Q5 D4 D5 N N Q6 OUT
N
N V VP FROM DECODE
ENABLE TO N-CHANNEL DEVICE OF THE SWITCH PAIR TO P-CHANNEL DEVICE OF THE SWITCH PAIR
FIGURE 5. ADDRESS DECODER
FIGURE 6. MULTIPLEX SWITCH
Burn-In/Life Test Circuits
V1 F0 F3 V1 D1 C1 1 2 3 4 5 6 R1 7 8 16 15 14 13 12 11 10 9 D2 C2 V2 F1 F2 V2 D1 C1 1 2 3 4 5 6 R1 7 8 16 15 14 13 12 11 10 9 D2 C2 V3
HS-0548RH DYNAMIC BURN-IN AND LIFE TEST CIRCUIT V1 V2 R1 C1 D1 F0 F1 F2 F3 = = = = = = = = = -15V maximum, -16V minimum +15V minimum, +16V maximum 10k ±5% 1/4W C2 = 0.01µF minimum (per socket) or 0.1µF minimum (per row) D2 = 1N4002 (or equivalent) 100kHz 50% duty cycle; VIL = 0.8V Max; VIH = 4.0V Min. F0/2 F1/2 F2/2 V1 V2 V3 R1 C1 = = = = =
HS-0548RH STATIC BURN-IN TEST CIRCUIT 5V minimum, 6V maximum -15V maximum, -16V minimum +15V minimum, +16V maximum 10k ±5% 1/4W C2 = 0.01µF minimum (per socket) or 0.1µF minimum (per row) D1 = D2 = 1N4002 (or equivalent)
4
HS-0548RH, HS-0549RH Burn-In/Life Test Circuits
(Continued)
F0 F2 V3 D1 C1
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
F1
1 2 V2 V3 D1 C1 3 4
16 15 14 13 12 11 10 9
V1
V2 D1 C1
D1
C1
5 6 7 8
R1
R1
R1
R1
HS-0549RH DYNAMIC BURN-IN AND LIFE TEST CIRCUIT V2 V3 R1 C1 D1 F0 = = = = = = +15.5V, ±.0.5V -15.5V, ±0.5V 10k, ±5% 0.01µF minimum (per socket) 1N4002 or equivalent (per board) 100kHz, ±10%; F1 = F0/2; F2 = F1/2 , 50% duty cycle, VIL = 0.8V Max; VIH = 4.0V Min V1 V2 V3 R1 C1 D1 = = = = = =
HS-0549RH STATIC BURN-IN TEST CIRCUIT +5.5V, ±0.5V +15.5V, ±0.5V -15.5V, ±0.5V 10k, ±10% 0.01µF minimum (per socket) 1N4002 or equivalent (per board)
Irradiation Circuits
+5V
1 2
16 15 14 13 12 11 10 9 R2 +15V +1V
+5V
1 2
16 15 14 13 12 11 10 9 +15V +1V
-15V +1V
3 4 5 6 7 8 R1
-15V +1V
3 4 5 6 7 8 R1
HS-0549RH R1 = R2 = 10k ±5%
HS-0548RH R1 = 10k ±5%
5
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