|Description||Radiation Hardened Real Time Express Microcontroller|
|Datasheet||Download 5962F9563501QXC datasheet
Radiation Hardened Real Time ExpressTM Microcontroller
The is a radiation-hardened 16-bit microcontroller with on-chip timers, an interrupt controller, a multiply-accumulator, and a barrel shifter. It is particularly well suited for space craft environments where very high speed control tasks which require arithmetically intensive calculations, including floating point math to be performed in hostile space radiation environments. This processor incorporates two 256-word stacks with multitasking capabilities, including configurable stack partitioning and over/underflow control. Instruction execution times of one or two machine cycles are achieved by utilizing a stack oriented, multiple bus architecture. The high performance ASIC Bus, which is unique to the RTX product, provides for extension of the microcontroller architecture using off-chip hardware and application specific I/O devices. RTX Microcontrollers support the C and Forth programming languages. The advantages of this product are further enhanced through third party hardware and software support. Combined, these features make the HS-RTX2010RH an extremely powerful processor serving numerous applications in high performance space systems. The HS-RTX2010RH has been designed for harsh space radiation environments and features outstanding Single Event Upset (SEU) resistance and excellent total dose response. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95635. A "hot-link" is provided on our homepage for downloading. www.intersil.com/spacedefense/space.aspFeatures
Electrically Screened to SMD # 5962-95635 QML Qualified per MIL-PRF-38535 Requirements Fast 125ns Machine Cycle 1.2µM TSOS4 CMOS/SOS Process Total Dose Capability. 300KRad(Si) Single Event Upset Critical LET. >120MeV/mg/cm2 Single Event Upset Error Rate. x 10-10 Errors/Bit-Day (Note) 5V ±10% Operation Single Cycle Instruction Execution Fast Arithmetic Operations - Single Cycle 16-Bit Multiply - Single Cycle 16-Bit Multiply Accumulate - Single Cycle 32-Bit Barrel Shift - Hardware Floating Point Support C Software Development Environment Direct Execution of Fourth Language Single Cycle Subroutine Call/Return Four Cycle Interrupt Latency On-Chip Interrupt Controller Three On-Chip 16-Bit Timer/Counters Two On-Chip 256 Word Stacks ASIC BusTM for Off-Chip Architecture Extension 1 Megabyte Total Address Space Word and Byte Memory Access Fully Static Design to 8MHz Operation 84 Lead Quad Flat Package or 85 Pin Grid Array Third Party Software and Hardware Development Systems
NOTE: Single Event Upset error rates are Adams 10% worst case environment under worst case conditions for upset.
ORDERING NUMBER 5962F9563501VXC 5962F9563501VYC INTERNAL MKT. NUMBER HS8-RTX2010RH-Q HS9-RTX2010RH-Q TEMP. RANGE (oC) to 125Applications
Space Systems Embedded Control Digital Filtering Image Processing Scientific Instrumentation Optical Systems Control Systems Attitude/Orbital Control
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Copyright © Intersil Corporation 2000 Real Time ExpressTM, RTXTM, and ASIC BusTM are trademarks of Intersil Corporation.
MA16 MA19 GND UDS PCLK MD01 MD02 GND MD11 MD09 VDD MD05 MD03 NEW BOOT LDS MA17 MA18 LDS BOOT NEW MD03 MD05 VDD HS-RTX2010RH 6 TCLK GND GA02 5 INTA 4 VDD E I2 NMI GD11 GD10 INTSUP TOP VIEW PINS DOWN GD11 GD14 INTSUP NMI INTA 4 ALIGN. PIN E I1 VDD GD12 GD13 GIO WAIT RESET I5 A PIN A1 ICLK GR/W GD15 GND GD07 GD09 VDD GD05 GD04 GND GD04 GD05 VDD GD09 GD07 GND GD15 GR/W ICLK E I5 PIN MD04 MD00 MR/W MA15 VDD MA13 MA12 GND MA09 MA10 GND BOTTOM VIEW PINS UP GA02 GND TCLK 6 MA15 MR/W 9 10NOTE: An overbar on a signal name represents an active LOW signal.
(Continued) HS9-RTX2010RH (LEAD LENGTH NOT TO SCALE) SEE INTERSIL OUTLINE R84.A
CQFP PGA PIN F3 G3 SIGNAL NAME GA02 TCLK INTA NMI INTSUP VDD EI4 EI5 RESET WAIT ICLK GR/W GIO GD14 GD13 GND GD11 GD10 TYPE Output; Address Bus Output Input Power Input Output I/O; Data Bus I/O; Data Bus I/O; Data Bus Ground I/O; Data Bus I/O; Data Bus I/O; Data Bus
I/O; Data Bus I/O; Data Bus I/O; Data Bus Power I/O; Data Bus I/O; Data Bus I/O; Data Bus I/O; Data Bus Ground I/O; Data Bus I/O; Data Bus I/O; Data Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Ground Output; Address Bus Output; Address Bus
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