Details, datasheet, quote on part number: 5962F9670301VXC
Part5962F9670301VXC
CategoryLogic => Gates
DescriptionRadiation Hardened Quad 2-input NAND Gate With Open Drain
CompanyIntersil Corporation
DatasheetDownload 5962F9670301VXC datasheet
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Features, Applications

Radiation Hardened Quad 2-Input NAND Gate with Open Drain
14 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C TOP VIEW
Features

Devices QML Qualified in Accordance with MIL-PRF-38535 Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96703 and Intersil's QM Plan 1.25 Micron Radiation Hardened SOS CMOS Total Dose. >300K RAD (Si) Single Event Upset (SEU) Immunity: x 10-10 Errors/Bit/Day (Typ) SEU LET Threshold. >100 MEV-cm2/mg Dose Rate Upset. >1011 RAD (Si)/s, 20ns Pulse Dose Rate Survivability. >1012 RAD (Si)/s, 20ns Pulse Latch-Up Free Under Any Conditions Military Temperature Range. to +125oC Significant Power Reduction Compared to ALSTTL Logic DC Operating Voltage Range. to 5.5V Input Logic Levels - VIL 30% of VCC Max - VIH 70% of VCC Min Input Current 1A at VOL, VOH Fast Propagation Delay. 15ns (Max), 10ns (Typ)

14 PIN CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C TOP VIEW
Description

The Intersil is a Radiation Hardened quad 2-input NAND gate with open drain outputs. The open drain output can drive resistive loads from a separate supply voltage. The ACS03MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic Family. The ACS03MS is supplied a 14 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line Package (D suffix).

PART NUMBER ACS03K/Sample ACS03HMSR TEMPERATURE RANGE +125oC 25oC SCREENING LEVEL MIL-PRF-38535 Class V MIL-PRF-38535 Class V Sample Die PACKAGE 14 Lead SBDIP 14 Lead Ceramic Flatpack 14 Lead SBDIP 14 Lead Ceramic Flatpack Die

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com 407-727-9207 | Copyright Intersil Corporation 1999

TRUTH TABLE INPUTS An NOTES: L = Low, H = High, Z = High Impedance 2. Without Pull-up Resistor 3. With Pull-up Resistor Bn OUTPUT Yn Z (Note 2), H (Note 3) Z (Note 2), H (Note 3) Z (Note 2), H (Note 3) L

DIE DIMENSIONS: 68 mils x 79 mils x 2010mm METALLIZATION: Type: AlSi Metal 1 Thickness: 7.125k 1.125k Metal 2 Thickness: 9k 1k GLASSIVATION: Type: SiO2 Thickness: 8k 1k WORST CASE CURRENT DENSITY: x 105A/cm2 BOND PAD SIZE: 110m 4.3 mils x 4.3 mils


 

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