16 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835, DESIGNATOR CDIP2-T16, LEAD FINISH C TOP VIEW
· Devices QML Qualified in Accordance with MIL-PRF-38535· Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96704 and Intersil'sIntersil QM Plan· 1.25 Micron Radiation Hardened SOS CMOS· Total Dose. >300K RAD (Si)· Single Event Upset (SEU) Immunity: x 10 (Typ)
· Dose Rate Survivability. >1012 RAD (Si)/s, 20ns Pulse· Latch-Up Free Under Any Conditions· Military Temperature Range. to +125oC· Significant Power Reduction Compared to ALSTTL Logic· DC Operating Voltage Range. to 5.5V· Input Logic Levels - VIL 30% of VCC Max - VIH 70% of VCC Min· Input Current 1µA at VOL, VOH· Fast Propagation Delay. 21ns (Max), 14ns (Typ)
16 PIN CERAMIC FLATPACK MIL-STD-1835, DESIGNATOR CDFP4-F16, LEAD FINISH C TOP VIEW
The Intersil is a Radiation Hardened Dual J-K Flip-Flop with Set and Reset. The output change states on the negative transition of the clock or CP2N). The ACS112MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hardened, high-speed, CMOS/SOS Logic Family. The ACS112MS is supplied a 16 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line Package (D suffix).
PART NUMBER ACS112K/Sample ACS112HMSR TEMPERATURE RANGE +125oC 25oC SCREENING LEVEL MIL-PRF-38535 Class V MIL-PRF-38535 Class V Sample Die PACKAGE 16 Lead SBDIP 16 Lead Ceramic Flatpack 16 Lead SBDIP 16 Lead Ceramic Flatpack Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com 407-727-9207 | Copyright © Intersil Corporation 1999