16 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835, DESIGNATOR CDIP2-T16, LEAD FINISH C TOP VIEW
Features
· Devices QML Qualified in Accordance with MIL-PRF-38535· Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96706 and Intersil' QM Plan· 1.25 Micron Radiation Hardened SOS CMOS· Total Dose. >300K RAD (Si)· Single Event Upset (SEU) Immunity: x 10 (Typ)
· Dose Rate Upset. >1011 RAD (Si)/s, 20ns Pulse· Dose Rate Survivability. >1012 RAD (Si)/s, 20ns Pulse· Latch-Up Free Under Any Conditions· Military Temperature Range. to +125oC· Significant Power Reduction Compared to ALSTTL Logic· DC Operating Voltage Range. to 5.5V· Input Logic Levels - VIL 30% of VCC Max - VIH 70% of VCC Min· Input Current 1µA at VOL, VOH· Fast Propagation Delay. 21ns (Max), 14ns (Typ)
16 PIN CERAMIC FLATPACK MIL-STD-1835, DESIGNATOR CDFP4-F16, LEAD FINISH C TOP VIEW
Description
The Intersil is a Radiation Hardened 4-Bit Binary Synchronous Counter. The is an active low master reset. SPE is an active low Synchronous Parallel Enable which disables counting and allows data at the preset inputs P3) to load the counter. CP is the positive edge clock. TC is the terminal count or carry output. Both TE and PE must be high for counting to occur, but are irrelevant to loading. TE low will keep TC low. The ACS161MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic family. The ACS161MS is supplied a 16 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line Package (D suffix).
PACKAGE 16 Lead SBDIP 16 Lead Ceramic Flatpack 16 Lead SBDIP 16 Lead Ceramic Flatpack Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com 407-727-9207 | Copyright © Intersil Corporation 1999
TRUTH TABLE INPUTS OPERATING MODE Reset (Clear) Parallel Load L H Count Inhibit X PE (Note X TE (Note 2) SPE (Note 3) h (Note 3) h (Note 3) PN
H = High Steady State, L = Low Steady State, h = High voltage level one setup time prior to the Low-to-High clock transition, I = Low voltage level one setup time prior to the Low-to-High clock transition, X = Don't Care,q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition, = Low-to-High Transition. NOTES: 1. The TC output is High when TE is High and the counter is at Terminal Count (HHHH). 2. The High-to-Low transition or TE should only occur while ZCP is High for conventional operation. 3. The Low-to-High transition of SPE should only occur while CP is High for conventional operation. 4. The TC output is High when TE is High and the counter is at Terminal Count (HHHH).
DIE DIMENSIONS: 88 mils x 88 mils x 2240mm METALLIZATION: Type: AlSi Metal 1 Thickness: 7.125kÅ ±1.125kÅ Metal 2 Thickness: 9kÅ ±1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ WORST CASE CURRENT DENSITY: x 105A/cm2 BOND PAD SIZE: 110µm 4.3 mils x 4.3 mils
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