|Category||Logic => Error Detection/Correction|
|Description||Radiation Hardened Edac ( Error Detection And Correction Circuit )|
|Datasheet||Download 5962F9671101VXC datasheet
|Cross ref.||Similar parts: CD40147B, CD4063B, CD4532B, CD4585B, CD74AC283, SN54F283, SN74F521|
Radiation Hardened EDAC (Error Detection and Correction Circuit)
28 PIN CERAMIC DUAL-IN-LINE, MIL-STD-1835 DESIGNATOR CDIP2-T28, LEAD FINISH C TOP VIEW
Devices QML Qualified in Accordance with MIL-PRF-38535 Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96711 and Intersil' QM Plan 1.25 Micron Radiation Hardened SOS CMOS Total Dose. >300K RAD (Si) Single Event Upset (SEU) Immunity: x 10 (Typ) Dose Rate Upset. >10 Dose Rate Survivability. >10 Latch-Up Free Under Any Conditions Military Temperature Range. +125 C
Significant Power Reduction Compared to ALSTTL Logic DC Operating Voltage Range. to 5.5V Input Logic Levels - VIL 30% of VCC Max - VIH 70% of VCC Min Input Current 1µA at VOL, VOH Fast Propagation Delay. 37ns (Max), 24ns (Typ)Description
The Intersil is a Radiation Hardened 16-bit parallel error detection and correction circuit. It uses a modified Hamming code to generate a 6-bit check word from each 16-bit data word. The check word is stored with the data word during a memory write cycle; during a memory read cycle a 22-bit word is taken form memory and checked for errors. Single bit errors in the data words are flagged and corrected. Single bit errors in check words are flagged but not corrected. The position of the incorrect bit is pinpointed, in both cases, by the 6-bit error syndrome code which is output during the error correction cycle. The ACS630MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic Family. The ACS630MS is supplied a 28 lead Ceramic Flatpack (K suffix) a 28 Lead Ceramic Dual-In-Line Package (D suffix).28 PIN CERAMIC FLATPACK, MIL-STD-1835 DESIGNATOR CDFP3-F28, LEAD FINISH C TOP VIEW
PACKAGE 28 Lead SBDIP 28 Lead Ceramic Flatpack 28 Lead SBDIP 28 Lead Ceramic Flatpack Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com 407-727-9207 | Copyright © Intersil Corporation 1999MEMORY CYCLE CONTROL S1 S0 EDAC FUNCTION DATA I/O CHECKWORD ERROR FLAGS SEF DEF
Generates Checkword Read Data and Checkword Latch and Flag Error Correct Data Word and Generate Syndrome BitsInput Data Input Data Latch Data Output Corrected Data
Output Checkword Input Checkword Latch Checkword Output Syndrome Bits
NOTE: The six check bits are parity bits derived from the matrix of data bits as indicated by "x" for each bitERROR LOCATIONS SYNDROME ERROR CODE CB NO ERROR
TOTAL NUMBER OF ERRORS 16-BIT DATA 6-BIT CHECKWORD SEF Low High ERROR FLAGS DEF Low High DATA CORRECTION Not Applicable Correction Interrupt
DIE DIMENSIONS: 171 mils x 159 mils x 4040mm METALLIZATION: Type: AlSi Metal 1 Thickness: 7.125kÅ ±1.125kÅ Metal 2 Thickness: 9kÅ ±1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ WORST CASE CURRENT DENSITY: x 105A/cm2 BOND PAD SIZE: 110µm 4.4 mils x 4.4 mils
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