|Description||Radiation Hardened Inverting, Octal, Three-state Buffer/line Driver|
|Datasheet||Download 5962F9854001VRC datasheet
|Cross ref.||Similar parts: CD54AC240F3A, CD74AC240E, 5962-8755001RA, SN74AC240N, 74AC11240, 74AC11244, 74AC11245, CD54AC244, CD54AC374, CD54ACT245|
Radiation Hardened Inverting, Octal, Three-State Buffer/Line Driver
The Radiation Hardened is an Inverting, Octal, Three-State Buffer/Line Driver with two active-LOW Enable inputs (AE and BE). Each Enable input controls four outputs. When an Enable input is LOW, the corresponding outputs are active and input signals are inverted. A HIGH on an Enable input causes the corresponding outputs to be high impedance, regardless of the input levels. The ACS240MS is fabricated on a CMOS Silicon on Sapphire (SOS) process, which provides an immunity to Single Event Latch-up and the capability of highly reliable performance in any radiation environment. These devices offer significant power reduction and faster performance when compared to ALSTTL types. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the ACS240 are contained in SMD 5962-98540. A "hot-link" is provided on our homepage with instructions for downloading. http://www.intersil.com/data/sm/index.htmFeatures
QML Qualified Per MIL-PRF-38535 Requirements 1.25Micron Radiation Hardened SOS CMOS Radiation Environment - Latch-up Free Under any Conditions - Total Dose. x 105 RAD(Si) - SEU Immunity. x 10-10 Errors/Bit/Day - SEU LET Threshold. >100MeV/(mg/cm2) Input Logic Levels VIL = (0.3V)(VCC), VIH = (0.7V)(VCC) Output Current. ±16mA Quiescent Supply Current.20µA Propagation Delay. 11.5nsApplications
Databus Driving Data Routing Redundant Data Control Circuitry
SMD PART NUMBER 5962F9854001VRC N/A 5962F9854001VXC N/A INTERSIL PART NUMBER ACS240K/Sample-02 ACS240HMSR-02 TEMP. RANGE (oC) 125 25 PACKAGE 20 Ld SBDIP 20 Ld SBDIP 20 Ld Flatpack 20 Ld Flatpack Die CASE OUTLINE CDIP2-T20 CDFP4-F20 N/A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Copyright © Intersil Corporation 1999
DIE DIMENSIONS: Size: 2540µm (100 mils x 100mils) Thickness: ±25µm (20.6 mils ±1 mil) Bond Pad: x 4.3 mils) METALLIZATION: Al Metal 1 Thickness: 0.7µm ±0.1µm Metal 2 Thickness: 1.0µm ±0.1µm SUBSTRATE POTENTIAL: Unbiased Insulator PASSIVATION Type: Phosphorous Silicon Glass (PSG) Thickness: 1.30µm ±0.15µm SPECIAL INSTRUCTIONS: Bond VCC First ADDITIONAL INFORMATION: Worst Case Density: 105 A/cm2 Transistor Count: 198
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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