|Category||Logic => Gates => NOR Gates|
|Description||Radiation Hardened Quad 2-input NOR GATE|
|Datasheet||Download 5962F9860101V9A datasheet
The Radiation Hardened is a Quad 2-Input NOR Gate. For each gate, a HIGH level on either or B input results in a LOW level on the Y output. A LOW level on both the A and B inputs results in a HIGH level on the Y output. All inputs are buffered and the outputs are designed for balanced propagation delay and transition times. The ACS02MS is fabricated on a CMOS Silicon on Sapphire (SOS) process, which provides an immunity to Single Event Latch-up and the capability of highly reliable performance in any radiation environment. These devices offer significant power reduction and faster performance when compared to ALSTTL types. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the ACS02MS are contained in SMD 5962-98601. A "hot-link" is provided on our homepage with instructions for downloading. www.intersil.com/data/sm/index.aspFeatures
QML Qualified Per MIL-PRF-38535 Requirements 1.25 Micron Radiation Hardened SOS CMOS Radiation Environment - Latch-Up Free Under Any Conditions - Total Dose. x 105 RAD(Si) - SEU Immunity. x 10-10 Errors/Bit/Day - SEU LET Threshold. >100MeV/(mg/cm2) Input Logic Levels. VIL = (0.3)(VCC), VIH = (0.7)(VCC) Output Current. ±8mA (Min) Quiescent Supply Current. 100µA (Max) Propagation Delay. 12ns (Max)Applications
High Speed Control Circuits Sensor Monitoring Low Power Designs
ORDERING NUMBER ACS02K/SAMPLE-03 5962F9860101V9A INTERNAL MARKETING NUMBER ACS02K/SAMPLE-03 ACS02HMSR-03 TEMP. RANGE (oC) 125 25 PACKAGE 14 Ld SBDIP 14 Ld SBDIP 14 Ld Flatpack 14 Ld Flatpack Die DESIGNATOR CDIP2-T14 CDFP4-F14 N/A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Copyright © Intersil Corporation 1999
DIE DIMENSIONS: Size: 2390µm (94 mils x 94 mils) Thickness: ±25µm (20.6 mils ±1 mil) Bond Pad: x 4.3 mils) METALLIZATION: AI Metal 1 Thickness: 0.7µm ±0.1µm Metal 2 Thickness: 1.0µm ±0.1µm SUBSTRATE POTENTIAL Unbiased Insulator PASSIVATION: Type: Phosphorous Silicon Glass (PSG) Thickness: 1.30µm ±0.15µm SPECIAL INSTRUCTIONS Bond VCC First ADDITIONAL INFORMATION: Worst Case Current Density: 105 A/cm2 Transistor Count: 108
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.For information regarding Intersil Corporation and its products, see web site www.intersil.com
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