|Category||Logic => Schmitt Triggers|
|Description||Radiation Hardened Quad 2-input NAND Schmitt Trigger|
|Datasheet||Download 5962F9862501V9A datasheet
Radiation Hardened Quad 2-Input NAND Schmitt Trigger
The Radiation Hardened is a Quad 3-Input NAND Gate with Schmitt Trigger inputs. When any input to one of the gates at a LOW level, the corresponding Y output will be HIGH. A HIGH level on both inputs will cause the output for that gate to be LOW. The Schmitt Trigger input stage provides 400mV (Min) of hysteresis and permits input signals with longer rise times. All inputs are buffered and the outputs are designed for balanced propagation delay and transition times. The ACS132MS is fabricated on a CMOS Silicon on Sapphire (SOS) process, which provides an immunity to Single Event Latch-up and the capability of highly reliable performance in any radiation environment. These devices offer significant power reduction and faster performance when compared to ALSTTL types. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the ACS132MS are contained in SMD 5962-98625. A "hot-link" is provided on our homepage with instructions for downloading. http://www.intersil.com/data/sm/index.htmFeatures
QML Qualified Per MIL-PRF-38535 Requirements 1.25 Micron Radiation Hardened SOS CMOS Radiation Environment - Latch-Up Free Under any Conditions - Total Dose. x 105 RAD (Si) - SEU Immunity. x 10-10 Errors/Bit/Day - SEU LET Threshold. >100MeV/(mg/cm2) Input Logic Levels. VIL = (0.3)(VCC), VIH = (0.7)(VCC) Hysteresis Voltage. 400mV (Min) Output Current. ±8mA (Min) Quiescent Supply Current. 100µA (Max) Propagation Delay. 12ns (Max)Applications
High Speed Control Circuits Sensor Monitoring Low Power Designs
ORDERING NUMBER ACS132K/SAMPLE-03 5962F9862501V9A INTERNAL MKT. NUMBER ACS132K/SAMPLE-03 ACS132HMSR-03 TEMP. RANGE (oC) 125 25 PACKAGE 14 Ld SBDIP 14 Ld SBDIP 14 Ld Flatpack 14 Ld Flatpack Die DESIGNATOR CDIP2-T14 CDFP4-F14 N/A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Copyright © Intersil Corporation 1999
DIE DIMENSIONS: Size: 2390µm (94 mils x 94 mils) Thickness: 25µm (20.6 mils ± 1 mil) Bond Pad: x 4.3 mils) METALLIZATION: AL Metal 1 Thickness: ± 0.1µm Metal 2 Thickness: ± 0.1µm SUBSTRATE POTENTIAL: Unbiased Insulator PASSIVATION Type: Phosphorous Silicon Glass (PSG) Thickness: ± 0.15µm SPECIAL INSTRUCTIONS: Bond VCC First ADDITIONAL INFORMATION: Worst Case Current Density: 105 A/cm2 Transistor Count: 92
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