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Part: 82C284-12
Category:
Microprocessors
-> System Components
Description: Clock Generator And Ready Interface For 80C286
Company: Intersil Corporation
Datasheet: Download 82C284-12 datasheet File size : 1163 kB
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TM
82C284
Clock Generator and Ready Interface for 80C286 Processors
Description
The Intersil 82C284 is a clock generator/driver which provides clock signals for 80C286 processors and support components. It also contains logic to supply READY to the CPU from either asynchronous or synchronous sources and synchronous RESET from an asynchronous input with hysteresis.
March 1997
Features
· Generates System Clock for 80C286 Processors · Generates System Reset Output from Schmitt Trigger Input - Improved Hysteresis · Uses Crystal or External Signal for Frequency Source · Dynamically Switchable between Two Input Frequencies · Provides Local READY and MULTIBUS READY Synchronization · Static CMOS Technology · Single +5V Power Supply · Available in 18 Lead CerDIP Package
Ordering Information
PART NUMBER CD82C 284-12 ID82C284-10 ID82C284-12 TEMP. RANGE 0oC to +70oC -40oC to +85oC -40oC to +85oC P ACKAGE PKG. NO.
18 Ld CERDIP F18.3 18 Ld CERDIP F18.3 18 Ld CERDIP F18.3
Pinout
82C284 (CERDIP) TOP VIEW
Functional Diagram
RESET ARDY 1 18 VCC 17 ARDYEN 16 S1 15 S0 14 NC 13 PCLK 12 RESET 11 RES 10 CLK E FI F/C ARDYEN ARDY SRDYEN SRDY X1 X2 XTAL OSC M UX RES SYNCHRONIZER
RESET
S RDY 2 SRDYEN 3
RE ADY 4 EFI F/C X1 X2 G ND 5 6 7 8 9
CL K
SYNCHRONIZER
READY LOGIC
READY
S1 S0
PCLK GENERATOR
PCLK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1
FN2966.1
MULTIBUS
is a patented Intel bus.
82C284 Pin Description The following pin function descriptions are for the 82C284 clock generator.
PIN SYMBOL CL K NU MBER 10 TYPE O DESCRIPTION SYSTEM CLOCK: the signal used by the processor and support devices which must be synchronous with the processor. The frequency of the CLK output has twice the desired internal processor clock frequency. CLK can drive both TTL and CMOS level inputs. FREQUENCY/CRYSTAL SELECT: this pin selects the source for the CLK output. When there is a LOW level on this input, the internal crystal oscillator drives CLK. When there is a HIGH level on F/C, the EFI input drives the CLK input. This pin can be dynamically switched, which allows changing the processor CLK frequency while running for low-power operation, etc. CRYS TAL IN: the pin stop which parallel resonant, fundamental mode crystal is attached for the internal oscillator. When F/C is LOW, the internal oscillator will drive the CLK output at the crystal frequency. The crystal frequency must be twice the desired internal processor clock frequency. EXTERNAL FREQUENCY IN: drives CLK when the F/C input is HIGH. The EFI input frequency must be twice the desired internal processor clock frequency. PERIPHERAL CLOCK: the output which provides a 50% duty cycle clock with one-half the frequency of CLK. PCLK will be in phase with the internal processor clock following the first bus cycle after the processor has been reset. ASYNCHRONOUS READY ENABLE: an active LOW input which qualifies the ARDY input. ARDYEN selects ARDY as the source of READY for the current bus cycle. Inputs to ARDYEN may be applied asynchronously to CLK. Setup and hold times are given to assure a guaranteed response to synchronous outputs. ASY NCHRONOUS READY: an active LOW input used to terminate the current bus cycle. The ARDY input is qualified by ARDYEN. Inputs to ARDY may be applied asynchronously to CLK. Setup and hold times are given to assure a guaranteed response to synchronous outputs. SYNC HRONOUS READY ENABLE: an active LOW input which qualifies SRDY. SRDYEN selects SRDY as the source for READY to the CPU for the current bus cycle. Setup and hold time must be satisfied for proper operation. SYNC HRONOUS READY: an active LOW input used to terminate the current bus cycle. The SRDY input is qualified by the SRDYEN input. Setup and hold time must be satisfied for proper operation. READ Y: an active LOW output which signals to the processor that the current bus cycle is to be completed. The SRDY SRDYEN, ARDY, ARDYEN, S1, S0, and RES inputs control READY as explained later in the READY generator section. READY is an open drain output requiring an external pull-up resistor. STATUS: these inputs prepare the 82C284 for a subsequent bus cycle. S0 and S1 synchronize PCLK to the internal processor clock and control READY. Setup and hold times must be satisfied for proper operation RESE T: an active HIGH output which is derived from the RES input RESET is used to force the system into an initial state. When RESET is active, READY will be active (LOW). RESET IN: an active LOW input which generates the system reset signal (RESET). Signals to RES may be applied asynchronously to CLK. A Schmitt trigger input is provided on RES, so that an RC circuit can be used to provide a time delay. Setup and hold times are given to assure a guaranteed response to synchronous inputs. SYS TEM POWER: The +5V Power Supply Pin. A 0.1µF capacitor between VCC and GND is recommended for decoupling. SYSTEM GROUND: 0V
F/C
6
I
X1, X2
7, 8
I
EFI
5
I
PC LK
13
O
A RDYEN
17
I
A RDY
1
I
S RDYEN
3
I
S RDY
2
I
RE ADY
4
O
S0, S1
15,16
I
RE SET
12
O
RES
11
I
VCC GND
18
9
2
82C284 Functional Description
Introduction The 82C284 generates the clock, ready, and reset signals required for 80C286 processors and support components. The 82C284 is packaged in an 18-pin DIP and contains a crystal controlled oscillator, clock generator, peripheral clock generator, MULTIBUS® ready synchronization logic, and system reset generation logic. Clock Generator The CLK output provides the basic timing control for an 80C286 system. CLK has output characteristics sufficient to drive CMOS devices. CLK is generated by either an internal crystal oscillator, or an external source as selected by the F/C input pin. When F/C is LOW, the crystal oscillator drives the CLK output. When F/C is HIGH, the EFI input drives the CLK output. The F/C pin on the Intersil 82C284 is dynamically switchable. This allows the CLK frequency to the processor to be changed from one frequency to another in a running system. With this feature, a system can be designed which operates at maximum speed when needed, and then dynamically sw itched to a lower frequency to implement a low-power mode. The lower frequency can be anything down to, but excluding, DC. The following 3 conditions apply when dynamically switching the F/C pin (see Figure 1): 1) The CLK is stretched in the low portion of the 2 phase of its cycle during transition from one CLK frequency to the other (see Waveforms). 2) When switching CLK frequency sources, there is a maximum transition latency of 2.5 clock cycles of the frequency being switched to, from the time CLK freezes low, until CLK restarts at the new frequency (see Waveforms). The maximum latency from the time F/C is dynamically switched, to the time CLK freezes low, is 4 CLK cycles (see Waveforms).
3)
The following steps describe the sequence of events that transpire when F/C is dynamically switched: A) F/C switched from high (using EFI input) to low (using the crystal input X1 - see Figure 1A). 1) The state of F/C is sampled when both CLK and PCLK are high until a change is detected. 2) On the second following falling edge of PCLK, CLK is frozen low. 3) CLK restarts at the crystal frequency on the rising edge of Xl, after the second falling edge of X1. B) F/C switched from low (using the crystal input Xl) to high (using the EFI input - see Figure 1B). 1) The state of F/C is sampled when both CLK and PCLK are high until a change is detected. 2) On the second following falling edge of PCLK, CLK is frozen low. 3) CLK restarts at the EFI input frequency on the falling edge of EFl after the second rising edge of EFI.
1 1 CL K
2
1
2
1
2
PCLK
2
F/C
X1 3
FIGURE 1A. F/C SWITCHED FROM HIGH (USING EFI INPUT) TO LOW (USING THE CRYSTAL INPUT X1)
3
82C284
1
C LK
1
2
1 2
2
1
2
PC LK
F/C
EFI
3
FIGURE 1B. F/C SWITCHED FROM LOW (USING THE CRYSTAL INPUT X1) TO HIGH (USING THE EFI INPUT) FIGURE 1. DYNAMICALLY SWITCHING THE F/C PIN
The 82C284 provides a second clock output, PCLK, for peripheral devices. PCLK is CLK divided by two. PCLK has a duty cycle of 50% and CMOS output drive characteristics. PCLK is normally synchronized to the internal processor clock. After reset, the PCLK signal may be out of phase with the internal processor clock. The S1 and S0 signals of the first bus cycle are used to synchronize PCLK to the internal processor clock. The phase of the PCLK output changes by extending its HIGH time beyond one system clock (see waveforms). PCLK is forced HIGH whenever either S0 or S1 were active (LOW) for the two previous CLK cycles. PCLK continues to oscillate when both S0 and S1 are HIGH. Since the phase of the internal processor clock will not change except during reset, the phase of PCLK will not change except during the first bus cycle after reset. Oscillator The oscillator circuit of the 82C284 is a linear Pierce oscillator which requires an external parallel resonant, fundamental mode, crystal. The output of the oscillator is internally buffered. The crystal frequency chosen should be twice the required internal processor clock frequency. The crystal should have a typical load capacitance of 32pF. X1 and X2 are the oscillator crystal connections. For stable operation of the oscillator, two loading capacitors are recommended, as shown in Table 1. The sum of the board capacitance and loading capacitance should equal the values shown. It is advisable to limit stray board capacitances (not including the effect of the loading capacitors or crystal capacitance) to less than 10pF between the X1 and X2 pins. Decouple VCC and GND as close to the 82C284 as possible with a 0.1µF polycarbonate capacitor.
TABLE 1. 82C284 CRYSTAL LOADING CAPACITANCE VALUES CRYSTAL FREQUE NCY 1MHz to 8MHz 8MHz to 20MHz 20MHz to 25MHz Cl CAPACITANCE (PIN 7) 60pF 25pF 15pF C2 CAPAC ITANCE (PIN 8) 40pF 15pF 15pF
CLK Termination Due to the CLK output having a very fast rise and fall time, it is recommended to properly terminate the CLK line at frequencies above 10MHz to avoid signal reflections and ringing. Termination is accomplished by inserting a small resistor (typically 10-74) in series with the output, as shown in Figure 2. This is known as series termination. The resistor value plus the circuit output impedance (approximately 25) should be made equal to the impedance of the transmission line.
CL K OUT R Z RO 25
CLOSELY PLACED L O ADS
TRAN SMISSION LINE Z CLOSELY PLACED L O ADS
FIGURE 2. SERIES TERMINATION
Reset Operation The reset logic provides the RESET output to force the system into a known, initial state. When the RES input is active (LOW), the RESET output becomes active (HIGH), RES is synchronized internally at the falling edge of CLK before generating the RESET output (see waveforms). Synchronization of the RES input introduces a one or two CLK delay before affecting the RESET Output. At power up, a system does not have a stable VCC and CLK. To prevent spurious activity, RES should be asserted until VCC and CLK stabilize at their operating values. 80C286 processors and support components also require their RESET inputs be HIGH a minimum of 16 CLK cycles. An RC network, as shown in Figure 3, will keep RES LOW long enough to satisfy both needs. A Schmitt trigger input with hysteresis on RES assures a single transition of RESET with an RC circuit on RES. The hysteresis separates the input voltage level at which the circuit output switches from HIGH to LOW from the input voltage level at which the circuit output switches from LOW to HIGH. The RES HIGH to LOW input transition voltage is lower than the RES
4
82C284
LOW to HIGH input transition voltage. As long as the slope of the RES input voltage remains in the same direction (increasing or decreasing) around the RES input transition voltage, the RESET output will make a single transition.
V CC C1 82C284 11 47 + 10 µF RES 6 F/C 7 10 V CC
X1 X2
CL K
CL K 80C28 6 CPU OR SUPPORT COMPONENT RE ADY VCC DECOUPLING CAPACITOR
8
82C28 4 READY VCC 4 18
1N914
10k
FIGURE 4. RECOMMENDED CRYSTAL AND READY CONDITIONS FIGURE 3. TYPICAL RC RES TIMING CIRCUIT
Ready Operation The 82C284 accepts two ready sources for the system ready signal which terminates the current bus cycle. Either a synchronous (SRDY) or asynchronous ready (ARDY) source may be used. Each ready input has an enable (SRDYEN and ARDYEN) for selecting the type of ready source required to terminate the current bus cycle. An address decoder would normally select one of the enable inputs. READY is enabled (LOW), if either SRDY + SRDYEN = 0 or ARDY + ARDYEN = 0 when sampled by the 82C284 READY generation logic. READY will remain active for at least two CLK cycles. The READY output has an open-drain driver allowing other ready circuits to be wired with it, as shown in Figure 4. The READY signal of an 80C286 system requires an external pull-up resistor. To force the READY signal inactive (HIGH) at the start of a bus cycle, the READY output floats when either S1 or S0 are sampled LOW at the falling edge of CLK. Two system clock periods are allowed for the pull-up resistor to pull the READY signal to VlH . When RESET is active, READY is forced active one CLK later (see Waveforms).
Figure 5 illustrates the operation of SRDY and SRDYEN. These inputs are sampled on the falling edge of CLK when S1 and S0 are inactive and PCLK is HIGH. READY is forced active when both SRDY and SRDYEN are sampled as LOW. Figure 6 shows the operation of ARDY and ARDYEN These inputs are sampled by an internal synchronizer at each falling edge of CLK. The output of the synchronizer is then sampled when PCLK is HIGH. If the synchronizer resolved both the ARDY and ARDYEN as active, the SRDY and SRDYEN inputs are ignored. Either ARDY or ARDYEN must be HIGH at the end of T S, therefore, at least one wait state is required when using the ARDY and ARDYEN inputs as a basis for generating READY. READY remains active until either S1 or S0 are sampled LOW, or the ready inputs are sampled as inactive.
5
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82-1 82-2
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