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Part: 82C37
Category:
Analog & Mixed-Signal Processing
Description: CMOS High Performance Programmable Dma Controller
Company: Intersil Corporation
Datasheet: Download 82C37 datasheet File size : 1163 kB
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TM
82C37A
CMOS High Performance Programmable DMA Controller
Description
The 82C37A is an enhanced version of the industry standard 8237A Direct Memory Access (DMA) controller, fabricated using Intersil's advanced 2 micron CMOS process. Pin com patible with NMOS designs, the 82C37A offers increased functionality, improved performance, and dramatically reduced power consumption. The fully static design permits gated clock operation for even further reduction of power. The 82C37A controller can improve system performance by allowing external devices to transfer data directly to or from system memory. Memory-to-memory transfer capability is also provided, along with a memory block initialization feature. DMA requests may be generated by either hardware or software, and each channel is independently programmable with a variety of features for flexible operation. The 82C37A is designed to be used with an external address latch, such as the 82C82, to demultiplex the most significant 8-bits of address. The 82C37A can be used with industry standard microprocessors such as 80C286, 80286, 80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and others. Multimode programmability allows the user to select from three basic types of DMA services, and reconfiguration under program control is possible even with the clock to the controller stopped. Each channel has a full 64K address and word count range, and may be programmed to autoinitialize these registers following DMA termination (end of process).
March 1997
Features
· Compatible with the NMOS 8237A · Four Independent Maskable Channels with Autoinitialization Capability · Cascadable to any Number of Channels · High Speed Data Transfers: - Up to 4MBytes/sec with 8MHz Clock - Up to 6.25MBytes/sec with 12.5MHz Clock · Memory-to-Memory Transfers · Static CMOS Design Permits Low Power Operation - ICCSB = 10µA Maximum - ICCOP = 2mA/MHz Maximum · Fully TTL/CMOS Compatible · Internal Registers may be Read from Software
Ordering Information
PART NUMBER 5 M Hz CP 82C37A-5 IP82C37A-5 CS 82C37A-5 IS82C37A-5 CD82C37A-5 ID82C37A-5 MD82C37A- 5/B 5962-9054301MQA MR82C37A- 5/B 5962-9054301MXA 8 M Hz CP82C37A IP82C37A CS 82C37A IS82C37A CD82C37A ID82C37A MD82C37A/B 5962-9054302MQA MR82C37A/B 5962-9054302MXA 12.5MHz CP 82C37A-12 IP82C37A-12 CS82C37A-12 IS82C37A-12 CD82C 37A-12 ID82C37A-12 MD82C37A- 12/B 5962-9054303MQA MR82C37A- 12/B 5962-9054303MXA SMD# 44 Pad CLCC SMD# -55oC to +125oC 40 Ld CERDIP 44 Ld PLCC PACKAGE 40 Ld PDIP TEMPERATURE RANGE 0oC to +70oC -40oC to +85oC 0oC to +70oC -40oC to +85oC 0oC to +70oC -40oC to +85oC -55oC to +125oC PKG. NO. E 40.6 E 40.6 N44.65 N44.65 F40.6 F40.6 F40.6 F40.6 J44.A J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN2967.1
192
82C37A Pinouts
82C37A (PDIP/CERDIP) TOP VIEW
READY
82C37A (CLCC/PLCC) TOP VIEW
MEMW MEMR EOP 39 A3 38 A2 37 A1 36 A0 35 VCC 34 DB0 33 DB1 32 DB2 31 DB3 30 DB4 29 NC 18 19 20 21 22 23 24 25 26 27 28 DREQ3 DREQ2 DREQ1 DREQ0 DB7 DB6 DACK3 DB5 DACK1 DACK0 GND IOW IOR
IOR IOW MEMR MEMW NC READY HL DA ADS T B AE N HRQ CS CL K R ESET DACK2 DACK3 DREQ3 DREQ2 DREQ1 DREQ0 (GND) VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 A7 39 A6 38 A5 37 A4 36 EOP 35 A3 34 A2 33 A1 32 A0 31 VCC 30 DB0 29 DB1 28 DB2 27 DB3 26 DB4 25 DACK0 24 DACK1 23 DB5 22 DB6 21 DB7
NC 7 NC 8 HLDA 9 ADSTB 10 AEN 11 HRQ 12 CS 13 CLK 14 RESET 15 DACK2 16 NC 17
NC
A7
A6
A5
6
5
4
3
2
1 44 43 42 41 40
Block Diagram
EOP RESET CS READY CL K AE N ADS T B MEMR MEMW IOR IOW TIMING AND CO NT RO L DECREMENTOR TEMP WORD COUN T REG (16) 16-BIT BUS 16-BIT BUS READ BUFFER BAS E ADDRESS (16) BAS E W O RD C OUNT (16) READ WRITE BUFFER CURRE NT ADDRESS (1 6) CURRE NT WORD COUNT (1 6) OUTPUT BUFFER INC/DECREMENTOR TEMP ADDRESS REG (16) IO BUFFER A0 - A3
A4
A4 - A7
A8 - A15
COMMAND CONTROL
WRI TE BUFFER DREQ0 DRE Q 3 HL DA HRQ DACK0 DACK3 4 4
R EAD BUFFER
D0 - D1
REQUEST (4)
MODE (4 x 6)
STATUS (8 )
TEMPORARY (8)
193
DB0 - DB7
PRIORITY ENCODER AND ROTATING PRIORITY LOGIC
COMMAND (8) MASK (4)
INTERNAL DATA BUS
IO BUFFER
82C37A Pin Description
SYMBOL VCC GND CL K PIN NUMBER 31 TYPE DESC RIPTION VCC: is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for decoupling. Ground I CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation. CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for CPU communications. RESE T: This is an active high input which clears the Command, Status, Request, and Temporary registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore requests. Following a Reset, the controller is in an idle cycle. READY : This signal can be used to extend the memory read and write pulses from the 82C37A to accommodate slow memories or I/O devices. READY must not make transitions during its specified set-up and hold times. See Figure 12 for timing. READY is ignored in verify transfer mode. HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has relinquished control of the system busses. HLDA is a synchronous input and must not transition during its specified set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising edge of CLK, during which time HLDA must not transition. DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a channel. DACK will acknowledge the recognition of a DREQ signal. Polarity of DREQ is progr ammable. RESET initializes these lines to active high. DREQ must be maintained until the corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set. DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data bus. The outputs are enabled in the Program condition during the I/O Read to output the contents of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle when the CPU is programming the 82C37A control registers. During DMA cycles, the most significant 8-bits of the address are output onto the data bus to be strobed into an external latch by ADSTB. In memory-to-memory operations, data from the memory enters the 82C37A on the data bus during the read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write the data into the new memory location. I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input control signal used by the CPU to read the control registers. In the Active cycle, it is an output control signal used by the 82C37A to access data from the peripheral during a DMA Write transfer. I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input control signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output control signal used by the 82C37A to load data to the peripheral during a DMA Read transfer.
20 12
CS
11
I
RE SET
13
I
RE ADY
6
I
HL DA
7
I
DREQ0DRE Q3
16-19
I
DB 0-DB 7
21-23 26-30
I/O
IOR
1
I/O
I OW
2
I/O
194
82C37A Pin Description
SYMBOL EOP PIN NUMBER 36 (Continued)
TYPE I/O
DESC RIPTION END OF PROCESS: End of Process (EOP) is an active low bidirectional signal. Information concerning the completion of DMA services is available at the bidirectional EOP pin. The 82C37A allows an external signal to terminate an active DMA service by pulling the EOP pin low. A pulse is generated by the 82C37A when terminal count (TC) for any channel is reached, except for channel 0 in memory-to-memory mode. During memory-to-memory transfers, EOP will be output when the TC for channel 1 occurs. The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor to VCC. When an EOP pulse occurs, whether internally or externally generated, the 82C37A will terminate the service, and if autoinitialize is enabled, the base registers will be written to the current registers of that channel. The mask bit and TC bit in the status word will be set for the currently active channel by EOP unless the channel is programmed for autoinitialize. In that case, the mask bit remains clear.
A 0-A 3
32-35
I/O
ADDRES S: The four least significant address lines are bidirectional three-state signals. In the Idle cycle, they are inputs and are used by the 82C37A to address the control register to be loaded or read. In the Active cycle, they are outputs and provide the lower 4-bits of the output address. ADDRES S: The four most significant address lines are three-state outputs and provide 4-bits of address. These lines are enabled only during the DMA service. HOLD REQUEST: The Hold Request (HRQ) output is used to request control of the system bus. When a DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made, the 82C37A issues HRQ. The HLDA signal then informs the controller when access to the system busses is permitted. For stand-alone operation where the 82C37A always controls the busses, HRQ may be tied to HLDA. This will result in one S0 state before the transfer. DMA ACKNOWLEDGE: DMA acknowledge is used to notify the individual peripherals when one has been granted a DMA cycle. The sense of these lines is programmable. RESET initializes them to active low. ADDRES S ENABLE: Address Enable enables the 8-bit latch containing the upper 8 address bits onto the system address bus. AEN can also be used to disable other system bus drivers during DMA transfers. AEN is active high. ADDRES S STROBE: This is an active high signal used to control latching of the upper address byte. It will drive directly the strobe input of external transparent octal latches, such as the 82C82. During block operations, ADSTB will only be issued when the upper address byte must be updated, thus speeding operation through elimination of S1 states. ADSTB timing is referenced to the falling edge of the 82C37A clock. MEMORY READ: The Memory Read signal is an active low three-state output used to access data from the selected memory location during a DMA Read or a memory-to-memory transfer. MEMORY WRITE: The Memory Write signal is an active low three-state output used to write data to the selected memory location during a DMA Write or a memory-to-memory transfer. NO CONNECT: Pin 5 is open and should not be tested for continuity.
A 4-A 7
37-40
O
HRQ
10
O
DACK0DA CK3
14, 15 24, 25
O
AEN
9
O
AD STB
8
O
MEMR
3
O
MEMW
4
O
NC
5
195
82C37A Functional Description
The 82C37A direct memory access controller is designed to improve the data transfer rate in systems which must transfer data from an I/O device to memory, or move a block of memory to an I/O device. It will also perform memory-tomemory block moves, or fill a block of memory with data from a single location. Operating modes are provided to handle single byte transfers as well as discontinuous data streams, which allows the 82C37A to control data movement with software transparency. The DMA controller is a state-driven address and control signal generator, which permits data to be transferred directly from an I/O device to memory or vice versa without ever being stored in a temporary register. This can greatly increase the data transfer rate for sequential operations, com pared with processor move or repeated string instructions. Memory-to-memory operations require temporary internal storage of the data byte between generation of the source and destination addresses, so memory-to-memory transfers take place at less than half the rate of I/O operations, but still much faster than with central processor techniques. The maximum data transfer rates obtainable with the 82C37A are shown in Figure 1. The block diagram of the 82C37A is shown on page 2. The tim ing and control block, priority block, and internal registers are the main components. Figure 2 lists the name and size of the internal registers. The timing and control block derives internal timing from clock input, and generates external control signals. The Priority Encoder block resolves priority contention between DMA channels requesting service simultaneously.
82C37A TRANSFER TYPE Compressed Normal I/O Memory-toMemory
For example, if a block of data is to be transferred from RAM to an I/O device, the starting address of the data is loaded into the 82C37A Current and Base Address registers for a particular channel, and the length of the block is loaded into the channel's Word Count register. The corresponding Mode register is programmed for a memory-to-I/O operation (read transfer), and various options are selected by the Command register and the other Mode register bits. The channel's mask bit is cleared to enable recognition of a DMA request (DREQ). The DREQ can either be a hardware signal or a software command. Once initiated, the block DMA transfer will proceed as the controller outputs the data address, simultaneous MEMR and IOW pulses, and selects an I/O device via the DMA acknowledge (DACK) outputs. The data byte flows directly from the RAM to the I/O device. After each byte is transferred, the address is automatically incremented (or decrem ented) and the word count is decremented. The operation is then repeated for the next byte. The controller stops transferring data when the Word Count register underflows, or an external EOP is applied.
NAM E Base Address Registers Base Word Count Registers Curr ent Address Registers Curr ent Word Count Registers Tempor ary Address Register SIZE 16-Bits 16-Bits 16-Bits 16-Bits 16-Bits 16-Bits 8-Bits 8-Bits 8-Bits 6-Bits 4-Bits 4-Bits NUMBER 4 4 4 4 1 1 1 1 1 4 1 1
5 M Hz 2.50 1.67 0.63
8 M Hz 4.00 2.67 1.00
12.5MHz 6.25 4.17 1.56
UN IT MByte/sec MByte/sec MByte/sec
Tempor ary Word Count Register Status Register Command Register Tempor ary Register Mode Registers
FIGURE 1. DMA TRANSFER RATES
Mask Register Request Register
DMA Operation
In a system, the 82C37A address and control outputs and data bus pins are basically connected in parallel with the system busses. An external latch is required for the upper address byte. While inactive, the controller's outputs are in a high impedance state. When activated by a DMA request and bus control is relinquished by the host, the 82C37A drives the busses and generates the control signals to perform the data transfer. The operation performed by activating one of the four DMA request inputs has previously been programmed into the controller via the Command, Mode, Address, and Word Count registers.
FIGURE 2. 82C37A INTERNAL REGISTERS
To further understand 82C37A operation, the states generated by each clock cycle must be considered. The DMA controller operates in two major cycles, active and idle. After being programmed, the controller is normally idle until a DMA request occurs on an unmasked channel, or a software request is given. The 82C37A will then request control of the system busses and enter the active cycle. The active cycle is com posed of several internal states, depending on what options have been selected and what type of operation has been requested.
196
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82-1 82-2
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